forked from OSchip/llvm-project
Add parentheses to silence warning
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@ -831,8 +831,8 @@ AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
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for (auto &MOP : MI.operands()) {
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if (MOP.isReg() && !MOP.isDebug() && MOP.getReg() &&
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TRI->regsOverlap(MOP.getReg(), RegToRename)) {
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assert(MOP.isImplicit() ||
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(MOP.isRenamable() && !MOP.isEarlyClobber()) &&
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assert((MOP.isImplicit() ||
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(MOP.isRenamable() && !MOP.isEarlyClobber())) &&
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"Need renamable operands");
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MOP.setReg(GetMatchingSubReg(MOP.getReg()));
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}
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