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[ARM] GlobalISel: Add more tests. NFC 

Add a couple of tests to increase coverage for the TableGen'erated code,
in particular for rules where 2 generic instructions may be combined
into a single machine instruction.

llvm-svn: 304971
This commit is contained in:
Diana Picus 2017-06-08 09:47:30 +00:00
parent da4a68a1d2
commit dbd4589042
1 changed files with 149 additions and 0 deletions
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149
llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir Normal file
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# RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @test_mla() #0 { ret void }
define void @test_mla_v5() #1 { ret void }
define void @test_mls() #2 { ret void }
define void @test_no_mls() { ret void }
attributes #0 = { "target-features"="+v6" }
attributes #1 = { "target-features"="-v6" }
attributes #2 = { "target-features"="+v6t2" }
...
---
name: test_mla
# CHECK-LABEL: name: test_mla
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: %r0, %r1, %r2
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2
; CHECK: [[VREGR:%[0-9]+]] = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
%r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_mla_v5
# CHECK-LABEL: name: test_mla_v5
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: %r0, %r1, %r2
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_ADD %3, %2
; CHECK: [[VREGR:%[0-9]+]] = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, _, _
%r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_mls
# CHECK-LABEL: name: test_mls
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: %r0, %r1, %r2
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3
; CHECK: [[VREGR:%[0-9]+]] = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, _
%r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_no_mls
# CHECK-LABEL: name: test_no_mls
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
- { id: 3, class: gprb }
- { id: 4, class: gprb }
body: |
bb.0:
liveins: %r0, %r1, %r2
%0(s32) = COPY %r0
%1(s32) = COPY %r1
%2(s32) = COPY %r2
; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
; CHECK: [[VREGZ:%[0-9]+]] = COPY %r2
%3(s32) = G_MUL %0, %1
%4(s32) = G_SUB %2, %3
; CHECK: [[VREGM:%[0-9]+]] = MULv5 [[VREGX]], [[VREGY]], 14, _, _
; CHECK: [[VREGR:%[0-9]+]] = SUBrr [[VREGZ]], [[VREGM]], 14, _, _
%r0 = COPY %4(s32)
; CHECK: %r0 = COPY [[VREGR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...