From dbcc4b4d4d82414885a384becebf9f3211763b94 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 24 Sep 2010 19:07:23 +0000 Subject: [PATCH] Enable code placement optimization pass for ARM. llvm-svn: 114746 --- llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 +-- llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll | 4 +- llvm/test/CodeGen/ARM/code-placement.ll | 51 ++++++++++++++++++- 3 files changed, 53 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index ae1fead462de..4c1e7af814ff 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -76,11 +76,6 @@ ARMInterworking("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true)); -static cl::opt -EnableARMCodePlacement("arm-code-placement", cl::Hidden, - cl::desc("Enable code placement pass for ARM"), - cl::init(false)); - void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT) { if (VT != PromotedLdStVT) { @@ -550,8 +545,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) // are at least 4 bytes aligned. setMinStackArgumentAlignment(4); - if (EnableARMCodePlacement) - benefitFromCodePlacementOpt = true; + benefitFromCodePlacementOpt = true; } std::pair diff --git a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll index 8d42a794feee..9085b6804c0e 100644 --- a/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -18,13 +18,13 @@ tailrecurse: ; preds = %sw.bb, %entry %0 = ptrtoint i8* %tmp2 to i32 ; CHECK: ands r12, r12, #3 -; CHECK-NEXT: beq LBB0_4 +; CHECK-NEXT: beq LBB0_2 ; T2: movs r5, #3 ; T2-NEXT: mov r6, r4 ; T2-NEXT: ands r6, r5 ; T2-NEXT: tst r4, r5 -; T2-NEXT: beq LBB0_5 +; T2-NEXT: beq LBB0_3 %and = and i32 %0, 3 %tst = icmp eq i32 %and, 0 diff --git a/llvm/test/CodeGen/ARM/code-placement.ll b/llvm/test/CodeGen/ARM/code-placement.ll index 25c556889fc4..bcf29ed9b46f 100644 --- a/llvm/test/CodeGen/ARM/code-placement.ll +++ b/llvm/test/CodeGen/ARM/code-placement.ll @@ -5,8 +5,9 @@ %struct.list_data_s = type { i16, i16 } %struct.list_head = type { %struct.list_head*, %struct.list_data_s* } -define arm_apcscc %struct.list_head* @t(%struct.list_head* %list) nounwind { +define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind { entry: +; CHECK: t1: %0 = icmp eq %struct.list_head* %list, null br i1 %0, label %bb2, label %bb @@ -27,3 +28,51 @@ bb2: %next.0.lcssa = phi %struct.list_head* [ null, %entry ], [ %list_addr.05, %bb ] ret %struct.list_head* %next.0.lcssa } + +; Optimize loop entry, eliminate intra loop branches +; rdar://8117827 +define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly { +entry: +; CHECK: t2: +; CHECK: beq LBB1_5 + %0 = icmp eq i32 %passes, 0 ; [#uses=1] + br i1 %0, label %bb5, label %bb.nph15 + +; CHECK: LBB1_2 +bb1: ; preds = %bb2.preheader, %bb1 +; CHECK: LBB1_3: +; CHECK: bne LBB1_3 + %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; [#uses=2] + %sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; [#uses=1] + %tmp17 = sub i32 %i.07, %indvar ; [#uses=1] + %scevgep = getelementptr i32* %src, i32 %tmp17 ; [#uses=1] + %1 = load i32* %scevgep, align 4 ; [#uses=1] + %2 = add nsw i32 %1, %sum.08 ; [#uses=2] + %indvar.next = add i32 %indvar, 1 ; [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %size ; [#uses=1] + br i1 %exitcond, label %bb3, label %bb1 + +bb3: ; preds = %bb1, %bb2.preheader +; CHECK: LBB1_4 +; CHECK: bne LBB1_2 +; CHECK-NOT: b LBB1_ +; CHECK: ldmia sp! + %sum.0.lcssa = phi i32 [ %sum.110, %bb2.preheader ], [ %2, %bb1 ] ; [#uses=2] + %3 = add i32 %pass.011, 1 ; [#uses=2] + %exitcond18 = icmp eq i32 %3, %passes ; [#uses=1] + br i1 %exitcond18, label %bb5, label %bb2.preheader + +bb.nph15: ; preds = %entry + %i.07 = add i32 %size, -1 ; [#uses=2] + %4 = icmp sgt i32 %i.07, -1 ; [#uses=1] + br label %bb2.preheader + +bb2.preheader: ; preds = %bb3, %bb.nph15 + %pass.011 = phi i32 [ 0, %bb.nph15 ], [ %3, %bb3 ] ; [#uses=1] + %sum.110 = phi i32 [ 0, %bb.nph15 ], [ %sum.0.lcssa, %bb3 ] ; [#uses=2] + br i1 %4, label %bb1, label %bb3 + +bb5: ; preds = %bb3, %entry + %sum.1.lcssa = phi i32 [ 0, %entry ], [ %sum.0.lcssa, %bb3 ] ; [#uses=1] + ret i32 %sum.1.lcssa +}