forked from OSchip/llvm-project
parent
6c2615177b
commit
dbc9ba3061
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@ -384,9 +384,9 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeRead2Pair(
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if (CI.BaseOff) {
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BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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BaseRegFlags = RegState::Kill;
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*BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg)
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.addImm(CI.BaseOff)
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.addReg(AddrReg->getReg());
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BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg)
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.addImm(CI.BaseOff)
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.addReg(AddrReg->getReg());
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}
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MachineInstrBuilder Read2 = BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg)
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@ -456,9 +456,9 @@ MachineBasicBlock::iterator SILoadStoreOptimizer::mergeWrite2Pair(
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if (CI.BaseOff) {
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BaseReg = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
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BaseRegFlags = RegState::Kill;
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*BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg)
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.addImm(CI.BaseOff)
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.addReg(Addr->getReg());
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BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::V_ADD_I32_e32), BaseReg)
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.addImm(CI.BaseOff)
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.addReg(Addr->getReg());
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}
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MachineInstrBuilder Write2 = BuildMI(*MBB, CI.Paired, DL, Write2Desc)
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