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Move MRI liveouts to AArch64 return instructions. 

llvm-svn: 174415
This commit is contained in:
Jakob Stoklund Olesen 2013-02-05 18:21:49 +00:00
parent 4af19d0014
commit dbc8c51acb
2 changed files with 12 additions and 14 deletions
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23
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -1035,15 +1035,8 @@ AArch64TargetLowering::LowerReturn(SDValue Chain,
// Analyze outgoing return values.
CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
// If this is the first return lowered for this function, add
// the regs to the liveout set for the function.
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
for (unsigned i = 0; i != RVLocs.size(); ++i)
if (RVLocs[i].isRegLoc())
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
}
SDValue Flag;
SmallVector<SDValue, 4> RetOps(1, Chain);
for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
// PCS: "If the type, T, of the result of a function is such that
@ -1087,13 +1080,17 @@ AArch64TargetLowering::LowerReturn(SDValue Chain,
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
Flag = Chain.getValue(1);
RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
}
if (Flag.getNode()) {
return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other, Chain, Flag);
} else {
return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other, Chain);
}
RetOps[0] = Chain; // Update chain.
// Add the flag if we have it.
if (Flag.getNode())
RetOps.push_back(Flag);
return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
&RetOps[0], RetOps.size());
}
SDValue

3
llvm/lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -6,7 +6,8 @@ include "AArch64InstrFormats.td"
def SDT_A64ret : SDTypeProfile<0, 0, []>;
def A64ret : SDNode<"AArch64ISD::Ret", SDT_A64ret, [SDNPHasChain,
SDNPOptInGlue]>;
SDNPOptInGlue,
SDNPVariadic]>;
// (ins NZCV, Condition, Dest)
def SDT_A64br_cc : SDTypeProfile<0, 3, [SDTCisVT<0, i32>]>;