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Rest of subtarget support, remove references to ppc 

llvm-svn: 25642
This commit is contained in:
Chris Lattner 2006-01-26 07:22:22 +00:00
parent e6842a9da6
commit dbc2aac1e7
4 changed files with 38 additions and 14 deletions
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34
llvm/lib/Target/SparcV8/SparcV8.td
View File

@ -17,12 +17,18 @@
include "../Target.td" include "../Target.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Subtarget features. // SPARC Subtarget features.
// //
def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit", def FeatureV9
"Enable 64-bit instructions">; : SubtargetFeature<"v9", "bool", "IsV9",
"Enable SPARC-V9 instructions">;
def FeatureV8Deprecated
: SubtargetFeature<"deprecated-v8", "bool", "V8DeprecatedInsts",
"Enable deprecated V8 instructions in V9 mode">;
def FeatureVIS
: SubtargetFeature<"vis", "bool", "IsVIS",
"Enable UltraSPARC Visual Instruction Set extensions">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register File Description // Register File Description
@ -48,9 +54,23 @@ def SparcV8InstrInfo : InstrInfo {
// SPARC processors supported. // SPARC processors supported.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : Processor<"generic", NoItineraries, []>; class Proc<string Name, list<SubtargetFeature> Features>
def : Processor<"v8", NoItineraries, []>; : Processor<Name, NoItineraries, Features>;
def : Processor<"v9", NoItineraries, [Feature64Bit]>;
def : Proc<"generic", []>;
def : Proc<"v8", []>;
def : Proc<"supersparc", []>;
def : Proc<"sparclite", []>;
def : Proc<"f934", []>;
def : Proc<"hypersparc", []>;
def : Proc<"sparclite86x", []>;
def : Proc<"sparclet", []>;
def : Proc<"tsc701", []>;
def : Proc<"v9", [FeatureV9]>;
def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Declare the target which we are implementing // Declare the target which we are implementing

8
llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -795,7 +795,7 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine /// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
/// instructions for SelectionDAG operations. /// instructions for SelectionDAG operations.
/// ///
namespace { namespace {
@ -816,7 +816,7 @@ public:
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
virtual const char *getPassName() const { virtual const char *getPassName() const {
return "PowerPC DAG->DAG Pattern Instruction Selection"; return "SparcV8 DAG->DAG Pattern Instruction Selection";
} }
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
@ -1011,8 +1011,8 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
} }
/// createPPCISelDag - This pass converts a legalized DAG into a /// createSparcV8ISelDag - This pass converts a legalized DAG into a
/// PowerPC-specific DAG, ready for instruction scheduling. /// SPARC-specific DAG, ready for instruction scheduling.
/// ///
FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
return new SparcV8DAGToDAGISel(TM); return new SparcV8DAGToDAGISel(TM);

2
llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
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@ -24,4 +24,4 @@ SparcV8Subtarget::SparcV8Subtarget(const Module &M, const std::string &FS) {
// Parse features string. // Parse features string.
ParseSubtargetFeatures(FS, CPU); ParseSubtargetFeatures(FS, CPU);
}; };

8
llvm/lib/Target/SparcV8/SparcV8Subtarget.h
View File

@ -21,11 +21,15 @@ namespace llvm {
class Module; class Module;
class SparcV8Subtarget : public TargetSubtarget { class SparcV8Subtarget : public TargetSubtarget {
bool Is64Bit; bool IsV9;
bool V8DeprecatedInsts;
bool IsVIS;
public: public:
SparcV8Subtarget(const Module &M, const std::string &FS); SparcV8Subtarget(const Module &M, const std::string &FS);
bool is64Bit() const { return Is64Bit; } bool isV9() const { return IsV9; }
bool isVIS() const { return IsVIS; }
bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
/// ParseSubtargetFeatures - Parses features string setting specified /// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen. /// subtarget options. Definition of function is auto generated by tblgen.