From dbc2aac1e7d25c15a2341a6d463ee58c6affb3da Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Thu, 26 Jan 2006 07:22:22 +0000
Subject: [PATCH] Rest of subtarget support, remove references to ppc

llvm-svn: 25642
---
 llvm/lib/Target/SparcV8/SparcV8.td            | 34 +++++++++++++++----
 .../Target/SparcV8/SparcV8ISelDAGToDAG.cpp    |  8 ++---
 llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp  |  2 +-
 llvm/lib/Target/SparcV8/SparcV8Subtarget.h    |  8 +++--
 4 files changed, 38 insertions(+), 14 deletions(-)

diff --git a/llvm/lib/Target/SparcV8/SparcV8.td b/llvm/lib/Target/SparcV8/SparcV8.td
index cd06886e1b71..886edc1c32a5 100644
--- a/llvm/lib/Target/SparcV8/SparcV8.td
+++ b/llvm/lib/Target/SparcV8/SparcV8.td
@@ -17,12 +17,18 @@
 include "../Target.td"
 
 //===----------------------------------------------------------------------===//
-// PowerPC Subtarget features.
+// SPARC Subtarget features.
 //
  
-def Feature64Bit     : SubtargetFeature<"64bit", "bool", "Is64Bit",
-                                        "Enable 64-bit instructions">;
-
+def FeatureV9
+  : SubtargetFeature<"v9", "bool", "IsV9",
+                     "Enable SPARC-V9 instructions">;
+def FeatureV8Deprecated
+  : SubtargetFeature<"deprecated-v8", "bool", "V8DeprecatedInsts",
+                     "Enable deprecated V8 instructions in V9 mode">;
+def FeatureVIS
+  : SubtargetFeature<"vis", "bool", "IsVIS",
+                     "Enable UltraSPARC Visual Instruction Set extensions">;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
@@ -48,9 +54,23 @@ def SparcV8InstrInfo : InstrInfo {
 // SPARC processors supported.
 //===----------------------------------------------------------------------===//
 
-def : Processor<"generic", NoItineraries, []>;
-def : Processor<"v8", NoItineraries, []>;
-def : Processor<"v9", NoItineraries, [Feature64Bit]>;
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
+
+def : Proc<"generic",         []>;
+def : Proc<"v8",              []>;
+def : Proc<"supersparc",      []>;
+def : Proc<"sparclite",       []>;
+def : Proc<"f934",            []>;
+def : Proc<"hypersparc",      []>;
+def : Proc<"sparclite86x",    []>;
+def : Proc<"sparclet",        []>;
+def : Proc<"tsc701",          []>;
+def : Proc<"v9",              [FeatureV9]>;
+def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
+
 
 //===----------------------------------------------------------------------===//
 // Declare the target which we are implementing
diff --git a/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index d8e6fb469ed6..6485ad2a2f5c 100644
--- a/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -795,7 +795,7 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
 //===----------------------------------------------------------------------===//
 
 //===--------------------------------------------------------------------===//
-/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
+/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
 /// instructions for SelectionDAG operations.
 ///
 namespace {
@@ -816,7 +816,7 @@ public:
   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
   
   virtual const char *getPassName() const {
-    return "PowerPC DAG->DAG Pattern Instruction Selection";
+    return "SparcV8 DAG->DAG Pattern Instruction Selection";
   } 
   
   // Include the pieces autogenerated from the target description.
@@ -1011,8 +1011,8 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
 }
 
 
-/// createPPCISelDag - This pass converts a legalized DAG into a 
-/// PowerPC-specific DAG, ready for instruction scheduling.
+/// createSparcV8ISelDag - This pass converts a legalized DAG into a 
+/// SPARC-specific DAG, ready for instruction scheduling.
 ///
 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
   return new SparcV8DAGToDAGISel(TM);
diff --git a/llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp b/llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
index 53a7b5bbeb20..5a08cd2bc4a2 100644
--- a/llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
+++ b/llvm/lib/Target/SparcV8/SparcV8Subtarget.cpp
@@ -24,4 +24,4 @@ SparcV8Subtarget::SparcV8Subtarget(const Module &M, const std::string &FS) {
   // Parse features string.
   ParseSubtargetFeatures(FS, CPU);
 
-};
\ No newline at end of file
+};
diff --git a/llvm/lib/Target/SparcV8/SparcV8Subtarget.h b/llvm/lib/Target/SparcV8/SparcV8Subtarget.h
index 682c99b16a4d..615d3d4fbc56 100644
--- a/llvm/lib/Target/SparcV8/SparcV8Subtarget.h
+++ b/llvm/lib/Target/SparcV8/SparcV8Subtarget.h
@@ -21,11 +21,15 @@ namespace llvm {
   class Module;
   
 class SparcV8Subtarget : public TargetSubtarget {
-  bool Is64Bit;
+  bool IsV9;
+  bool V8DeprecatedInsts;
+  bool IsVIS;
 public:
   SparcV8Subtarget(const Module &M, const std::string &FS);
 
-  bool is64Bit() const { return Is64Bit; }
+  bool isV9() const { return IsV9; }
+  bool isVIS() const { return IsVIS; }
+  bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
   
   /// ParseSubtargetFeatures - Parses features string setting specified 
   /// subtarget options.  Definition of function is auto generated by tblgen.