forked from OSchip/llvm-project
Rest of subtarget support, remove references to ppc
llvm-svn: 25642
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@ -17,12 +17,18 @@
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// PowerPC Subtarget features.
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// SPARC Subtarget features.
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//
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def Feature64Bit : SubtargetFeature<"64bit", "bool", "Is64Bit",
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"Enable 64-bit instructions">;
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def FeatureV9
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: SubtargetFeature<"v9", "bool", "IsV9",
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"Enable SPARC-V9 instructions">;
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def FeatureV8Deprecated
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: SubtargetFeature<"deprecated-v8", "bool", "V8DeprecatedInsts",
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"Enable deprecated V8 instructions in V9 mode">;
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def FeatureVIS
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: SubtargetFeature<"vis", "bool", "IsVIS",
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"Enable UltraSPARC Visual Instruction Set extensions">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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@ -48,9 +54,23 @@ def SparcV8InstrInfo : InstrInfo {
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// SPARC processors supported.
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//===----------------------------------------------------------------------===//
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def : Processor<"generic", NoItineraries, []>;
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def : Processor<"v8", NoItineraries, []>;
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def : Processor<"v9", NoItineraries, [Feature64Bit]>;
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"v8", []>;
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def : Proc<"supersparc", []>;
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def : Proc<"sparclite", []>;
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def : Proc<"f934", []>;
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def : Proc<"hypersparc", []>;
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def : Proc<"sparclite86x", []>;
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def : Proc<"sparclet", []>;
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def : Proc<"tsc701", []>;
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def : Proc<"v9", [FeatureV9]>;
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def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated]>;
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def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated]>;
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def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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@ -795,7 +795,7 @@ SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
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//===----------------------------------------------------------------------===//
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//===--------------------------------------------------------------------===//
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/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
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/// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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@ -816,7 +816,7 @@ public:
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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return "SparcV8 DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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@ -1011,8 +1011,8 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
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}
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/// createPPCISelDag - This pass converts a legalized DAG into a
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/// PowerPC-specific DAG, ready for instruction scheduling.
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/// createSparcV8ISelDag - This pass converts a legalized DAG into a
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/// SPARC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
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return new SparcV8DAGToDAGISel(TM);
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@ -24,4 +24,4 @@ SparcV8Subtarget::SparcV8Subtarget(const Module &M, const std::string &FS) {
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// Parse features string.
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ParseSubtargetFeatures(FS, CPU);
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};
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};
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@ -21,11 +21,15 @@ namespace llvm {
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class Module;
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class SparcV8Subtarget : public TargetSubtarget {
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bool Is64Bit;
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bool IsV9;
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bool V8DeprecatedInsts;
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bool IsVIS;
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public:
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SparcV8Subtarget(const Module &M, const std::string &FS);
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bool is64Bit() const { return Is64Bit; }
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bool isV9() const { return IsV9; }
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bool isVIS() const { return IsVIS; }
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bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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