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[ARM] Add cdp intrinsic tests. 

- Renamed intrinsics.ll to intrinsics-coprocessor.ll
  as all the tests were testing coprocessor instructions,
  also made the test checks match the full instruction.

Differential Revision: http://reviews.llvm.org/D20393

llvm-svn: 270057
This commit is contained in:
Ranjeet Singh 2016-05-19 12:59:17 +00:00
parent c520e93d9a
commit dbbbef5401
3 changed files with 34 additions and 8 deletions
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13
llvm/test/CodeGen/ARM/cdp.ll Normal file
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@ -0,0 +1,13 @@
; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp
define void @cdp(i32 %a) #0 {
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
%1 = load i32, i32* %a.addr, align 4
call void @llvm.arm.cdp(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
ret void
}
declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind

13
llvm/test/CodeGen/ARM/cdp2.ll Normal file
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@ -0,0 +1,13 @@
; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp2
define void @cdp2(i32 %a) #0 {
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
%1 = load i32, i32* %a.addr, align 4
call void @llvm.arm.cdp2(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6)
ret void
}
declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind

16
llvm/test/CodeGen/ARM/intrinsics.ll → llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll
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@ -3,21 +3,21 @@
define void @coproc() nounwind {
entry:
; CHECK: mrc
; CHECK: mrc p7, #1, r0, c1, c1, #4
%0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
; CHECK: mcr
; CHECK: mcr p7, #1, r0, c1, c1, #4
tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind
; CHECK: mrc2
; CHECK: mrc2 p7, #1, r1, c1, c1, #4
%1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind
; CHECK: mcr2
; CHECK: mcr2 p7, #1, r1, c1, c1, #4
tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind
; CHECK: mcrr
; CHECK: mcrr p7, #1, r0, r1, c1
tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
; CHECK: mcrr2
; CHECK: mcrr2 p7, #1, r0, r1, c1
tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind
; CHECK: cdp
; CHECK: cdp p7, #3, c1, c1, c1, #5
tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
; CHECK: cdp2
; CHECK: cdp2 p7, #3, c1, c1, c1, #5
tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind
ret void
}