forked from OSchip/llvm-project
[riscv] Add a couple more vsetvli tests
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@ -254,6 +254,53 @@ entry:
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ret <vscale x 1 x double> %0
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}
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define <vscale x 1 x double> @test14(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
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; CHECK-LABEL: test14:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, mu
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; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
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%f1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %a,
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<vscale x 1 x double> %b,
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i64 1)
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%f2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %f1,
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<vscale x 1 x double> %b,
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i64 %vsetvli)
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ret <vscale x 1 x double> %f2
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}
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define <vscale x 1 x double> @test15(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
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; CHECK-LABEL: test15:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, mu
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
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; CHECK-NEXT: ret
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entry:
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%vsetvli = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
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%f1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %a,
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<vscale x 1 x double> %b,
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i64 %avl)
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%f2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %f1,
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<vscale x 1 x double> %b,
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i64 %vsetvli)
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ret <vscale x 1 x double> %f2
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}
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declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
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<vscale x 1 x i64>,
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<vscale x 1 x i64>,
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