forked from OSchip/llvm-project
parent
3f73184d90
commit
dbb60f960a
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@ -152,7 +152,7 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
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(ops (i32 14), (i32 zero_reg))> {
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let PrintMethod = "printPredicateOperand";
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let ParserMatchClass = CondCodeOperand;
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let DecoderMethod = "DecodePredicateOperand";
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let DecoderMethod = "DecodePredicateOperand";
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}
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// Conditional code result for instructions whose 's' bit is set, e.g. subs.
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