forked from OSchip/llvm-project
[Hexagon] Generate HVX/FP arithmetic instructions
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com> Co-authored-by: Sumanth Gundapaneni <sgundapa@quicinc.com> Co-authored-by: Joshua Herrera <joshherr@quicinc.com>
This commit is contained in:
Krzysztof Parzyszek
parent
ee8e81b40e
commit
db83e3e507
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@ -93,6 +93,12 @@ HexagonTargetLowering::initializeHVXLowering() {
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Subtarget.useHVXFloatingPoint()) {
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setOperationAction(ISD::FMINNUM, MVT::v64f16, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::v64f16, Legal);
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setOperationAction(ISD::FADD, MVT::v64f16, Legal);
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setOperationAction(ISD::FSUB, MVT::v64f16, Legal);
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setOperationAction(ISD::FMUL, MVT::v64f16, Legal);
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setOperationAction(ISD::FADD, MVT::v32f32, Legal);
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setOperationAction(ISD::FSUB, MVT::v32f32, Legal);
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setOperationAction(ISD::FMUL, MVT::v32f32, Legal);
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setOperationAction(ISD::FMINNUM, MVT::v32f32, Legal);
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setOperationAction(ISD::FMAXNUM, MVT::v32f32, Legal);
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setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64f16, Custom);
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@ -126,6 +132,9 @@ HexagonTargetLowering::initializeHVXLowering() {
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setOperationAction(ISD::LOAD, MVT::v64f32, Custom);
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setOperationAction(ISD::STORE, MVT::v64f32, Custom);
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setOperationAction(ISD::FADD, MVT::v64f32, Custom);
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setOperationAction(ISD::FSUB, MVT::v64f32, Custom);
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setOperationAction(ISD::FMUL, MVT::v64f32, Custom);
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setOperationAction(ISD::FMINNUM, MVT::v64f32, Custom);
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setOperationAction(ISD::FMAXNUM, MVT::v64f32, Custom);
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setOperationAction(ISD::VSELECT, MVT::v64f32, Custom);
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@ -2291,6 +2300,9 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::CTLZ:
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case ISD::CTTZ:
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case ISD::MUL:
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case ISD::FADD:
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case ISD::FSUB:
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case ISD::FMUL:
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case ISD::FMINNUM:
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case ISD::FMAXNUM:
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case ISD::MULHS:
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@ -453,6 +453,52 @@ let Predicates = [UseHVX] in {
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(V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
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}
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// For now, we always deal with vector floating point in SF mode.
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class OpR_RR_pat_conv<InstHexagon MI, PatFrag Op, ValueType ResType,
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PatFrag RsPred, PatFrag RtPred = RsPred>
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: Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
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(V6_vconv_sf_qf32 (VecF32 (MI RsPred:$Rs, RtPred:$Rt)))>;
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class OpR_RR_pat_conv_hf<InstHexagon MI, PatFrag Op, ValueType ResType,
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PatFrag RsPred, PatFrag RtPred = RsPred>
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: Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
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(V6_vconv_hf_qf16 (VecF16 (MI RsPred:$Rs, RtPred:$Rt)))>;
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let Predicates = [UseHVXV68, UseHVXQFloat] in {
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def: OpR_RR_pat_conv_hf<V6_vsub_hf, pf2<fsub>, VecF16, HVF16>;
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def: OpR_RR_pat_conv_hf<V6_vadd_hf, pf2<fadd>, VecF16, HVF16>;
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def: OpR_RR_pat_conv_hf<V6_vmpy_qf16_hf, pf2<fmul>, VecF16, HVF16>;
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def: OpR_RR_pat_conv<V6_vsub_sf, pf2<fsub>, VecF32, HVF32>;
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def: OpR_RR_pat_conv<V6_vadd_sf, pf2<fadd>, VecF32, HVF32>;
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def: OpR_RR_pat_conv<V6_vmpy_qf32_sf, pf2<fmul>, VecF32, HVF32>;
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// For now we assume that the fp32 register is always coming in as IEEE float
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// since the qfloat arithmetic instructions above always generate the
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// accompanying conversions as part of their pattern
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def: Pat<(VecF16 (pf1<fpround> HWF32:$Vuu)),
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(V6_vdealh (V6_vconv_hf_qf32
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(VecPF32 (Combinev (V6_vadd_sf (HiVec HvxWR:$Vuu), (V6_vd0)),
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(V6_vadd_sf (LoVec HvxWR:$Vuu), (V6_vd0))
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))))>;
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}
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// HVX IEEE arithmetic Instructions
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let Predicates = [UseHVXV68, UseHVXIEEEFP] in {
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def: Pat<(fadd HVF16:$Rs, HVF16:$Rt),
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(V6_vadd_hf_hf HVF16:$Rs, HVF16:$Rt)>;
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def: Pat<(fadd HVF32:$Rs, HVF32:$Rt),
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(V6_vadd_sf_sf HVF32:$Rs, HVF32:$Rt)>;
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def: Pat<(fsub HVF16:$Rs, HVF16:$Rt),
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(V6_vsub_hf_hf HVF16:$Rs, HVF16:$Rt)>;
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def: Pat<(fsub HVF32:$Rs, HVF32:$Rt),
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(V6_vsub_sf_sf HVF32:$Rs, HVF32:$Rt)>;
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def: Pat<(fmul HVF16:$Rs, HVF16:$Rt),
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(V6_vmpy_hf_hf HVF16:$Rs, HVF16:$Rt)>;
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def: Pat<(fmul HVF32:$Rs, HVF32:$Rt),
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(V6_vmpy_sf_sf HVF32:$Rs, HVF32:$Rt)>;
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}
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let Predicates = [UseHVXV68, UseHVXFloatingPoint] in {
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def: Pat<(vselect HQ16:$Qu, HVF16:$Vs, HVF16:$Vt),
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(V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
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@ -0,0 +1,167 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=hexagon < %s | FileCheck %s
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define <64 x half> @f0(<64 x half> %a0, <64 x half> %a1) #0 {
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; CHECK-LABEL: f0:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.qf16 = vadd(v0.hf,v1.hf)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.hf = v0.qf16
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fadd <64 x half> %a0, %a1
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ret <64 x half> %v0
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}
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define <32 x float> @f1(<32 x float> %a0, <32 x float> %a1) #0 {
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; CHECK-LABEL: f1:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.qf32 = vadd(v0.sf,v1.sf)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.sf = v0.qf32
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fadd <32 x float> %a0, %a1
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ret <32 x float> %v0
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}
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define <64 x half> @f2(<64 x half> %a0, <64 x half> %a1) #0 {
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; CHECK-LABEL: f2:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.qf16 = vsub(v0.hf,v1.hf)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.hf = v0.qf16
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fsub <64 x half> %a0, %a1
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ret <64 x half> %v0
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}
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define <32 x float> @f3(<32 x float> %a0, <32 x float> %a1) #0 {
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; CHECK-LABEL: f3:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.qf32 = vsub(v0.sf,v1.sf)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.sf = v0.qf32
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fsub <32 x float> %a0, %a1
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ret <32 x float> %v0
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}
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define <64 x half> @f4(<64 x half> %a0, <64 x half> %a1) #0 {
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; CHECK-LABEL: f4:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.qf16 = vmpy(v0.hf,v1.hf)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.hf = v0.qf16
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fmul <64 x half> %a0, %a1
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ret <64 x half> %v0
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}
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define <32 x float> @f5(<32 x float> %a0, <32 x float> %a1) #0 {
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; CHECK-LABEL: f5:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.qf32 = vmpy(v0.sf,v1.sf)
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; CHECK-NEXT: }
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.sf = v0.qf32
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fmul <32 x float> %a0, %a1
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ret <32 x float> %v0
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}
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define <64 x half> @f6(<64 x half> %a0, <64 x half> %a1) #1 {
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; CHECK-LABEL: f6:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.hf = vadd(v0.hf,v1.hf)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fadd <64 x half> %a0, %a1
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ret <64 x half> %v0
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}
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define <32 x float> @f7(<32 x float> %a0, <32 x float> %a1) #1 {
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; CHECK-LABEL: f7:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.sf = vadd(v0.sf,v1.sf)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fadd <32 x float> %a0, %a1
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ret <32 x float> %v0
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}
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define <64 x half> @f8(<64 x half> %a0, <64 x half> %a1) #1 {
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; CHECK-LABEL: f8:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.hf = vsub(v0.hf,v1.hf)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fsub <64 x half> %a0, %a1
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ret <64 x half> %v0
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}
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define <32 x float> @f9(<32 x float> %a0, <32 x float> %a1) #1 {
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; CHECK-LABEL: f9:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.sf = vsub(v0.sf,v1.sf)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fsub <32 x float> %a0, %a1
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ret <32 x float> %v0
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}
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define <64 x half> @f10(<64 x half> %a0, <64 x half> %a1) #1 {
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; CHECK-LABEL: f10:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.hf = vmpy(v0.hf,v1.hf)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fmul <64 x half> %a0, %a1
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ret <64 x half> %v0
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}
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define <32 x float> @f11(<32 x float> %a0, <32 x float> %a1) #1 {
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; CHECK-LABEL: f11:
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; CHECK: // %bb.0: // %b0
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; CHECK-NEXT: {
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; CHECK-NEXT: v0.sf = vmpy(v0.sf,v1.sf)
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; CHECK-NEXT: jumpr r31
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; CHECK-NEXT: }
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b0:
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%v0 = fmul <32 x float> %a0, %a1
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ret <32 x float> %v0
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv69" "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" }
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attributes #1 = { nounwind "target-cpu"="hexagonv69" "target-features"="+hvxv69,+hvx-length128b,+hvx-ieee-fp" }
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