forked from OSchip/llvm-project
[AMDGPU] Vectorize alloca thru bitcast
This is mostly useful if alloca element type is not integer and then casted to an integer for load or store. We now can vectorize an [i32] alloca but cannot do so for [float]. There also a separate patch needed to properly lower 64 bit types after they vectorized. At the moment these are lowered via scratch anyway. Differential Revision: https://reviews.llvm.org/D79641
This commit is contained in:
Stanislav Mekhanoshin
parent
23cbea9a04
commit
db7dea2b6f
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@ -302,10 +302,19 @@ static VectorType *arrayTypeToVecType(ArrayType *ArrayTy) {
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ArrayTy->getNumElements());
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}
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static Value *stripBitcasts(Value *V) {
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while (Instruction *I = dyn_cast<Instruction>(V)) {
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if (I->getOpcode() != Instruction::BitCast)
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break;
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V = I->getOperand(0);
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}
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return V;
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}
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static Value *
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calculateVectorIndex(Value *Ptr,
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const std::map<GetElementPtrInst *, Value *> &GEPIdx) {
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GetElementPtrInst *GEP = cast<GetElementPtrInst>(Ptr);
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GetElementPtrInst *GEP = cast<GetElementPtrInst>(stripBitcasts(Ptr));
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auto I = GEPIdx.find(GEP);
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return I == GEPIdx.end() ? nullptr : I->second;
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@ -327,7 +336,8 @@ static Value* GEPToVectorIndex(GetElementPtrInst *GEP) {
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//
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// TODO: Check isTriviallyVectorizable for calls and handle other
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// instructions.
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static bool canVectorizeInst(Instruction *Inst, User *User) {
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static bool canVectorizeInst(Instruction *Inst, User *User,
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const DataLayout &DL) {
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switch (Inst->getOpcode()) {
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case Instruction::Load: {
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// Currently only handle the case where the Pointer Operand is a GEP.
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@ -337,7 +347,14 @@ static bool canVectorizeInst(Instruction *Inst, User *User) {
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LI->getPointerOperandType() == User->getType() &&
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isa<VectorType>(LI->getType()))
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return true;
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return isa<GetElementPtrInst>(LI->getPointerOperand()) && LI->isSimple();
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Instruction *PtrInst = dyn_cast<Instruction>(LI->getPointerOperand());
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if (!PtrInst)
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return false;
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return (PtrInst->getOpcode() == Instruction::GetElementPtr ||
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PtrInst->getOpcode() == Instruction::BitCast) &&
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LI->isSimple();
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}
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case Instruction::BitCast:
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return true;
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@ -350,14 +367,22 @@ static bool canVectorizeInst(Instruction *Inst, User *User) {
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SI->getPointerOperandType() == User->getType() &&
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isa<VectorType>(SI->getValueOperand()->getType()))
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return true;
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return (SI->getPointerOperand() == User) && isa<GetElementPtrInst>(User) && SI->isSimple();
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Instruction *UserInst = dyn_cast<Instruction>(User);
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if (!UserInst)
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return false;
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return (SI->getPointerOperand() == User) &&
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(UserInst->getOpcode() == Instruction::GetElementPtr ||
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UserInst->getOpcode() == Instruction::BitCast) &&
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SI->isSimple();
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}
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default:
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return false;
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}
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}
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static bool tryPromoteAllocaToVector(AllocaInst *Alloca) {
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static bool tryPromoteAllocaToVector(AllocaInst *Alloca, const DataLayout &DL) {
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if (DisablePromoteAllocaToVector) {
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LLVM_DEBUG(dbgs() << " Promotion alloca to vector is disabled\n");
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@ -385,13 +410,37 @@ static bool tryPromoteAllocaToVector(AllocaInst *Alloca) {
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}
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std::map<GetElementPtrInst*, Value*> GEPVectorIdx;
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std::vector<Value*> WorkList;
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for (User *AllocaUser : Alloca->users()) {
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std::vector<Value *> WorkList;
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SmallVector<User *, 8> Users(Alloca->users());
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SmallVector<User *, 8> UseUsers(Users.size(), Alloca);
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Type *VecEltTy = VectorTy->getElementType();
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while (!Users.empty()) {
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User *AllocaUser = Users.pop_back_val();
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User *UseUser = UseUsers.pop_back_val();
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Instruction *Inst = dyn_cast<Instruction>(AllocaUser);
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GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(AllocaUser);
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if (!GEP) {
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if (!canVectorizeInst(cast<Instruction>(AllocaUser), Alloca))
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if (!canVectorizeInst(Inst, UseUser, DL))
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return false;
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if (Inst->getOpcode() == Instruction::BitCast) {
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Type *FromTy = Inst->getOperand(0)->getType()->getPointerElementType();
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Type *ToTy = Inst->getType()->getPointerElementType();
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if (FromTy->isAggregateType() || ToTy->isAggregateType() ||
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DL.getTypeSizeInBits(FromTy) != DL.getTypeSizeInBits(ToTy))
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continue;
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for (User *CastUser : Inst->users()) {
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if (isAssumeLikeIntrinsic(cast<Instruction>(CastUser)))
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continue;
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Users.push_back(CastUser);
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UseUsers.push_back(Inst);
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}
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continue;
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}
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WorkList.push_back(AllocaUser);
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continue;
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}
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@ -407,12 +456,8 @@ static bool tryPromoteAllocaToVector(AllocaInst *Alloca) {
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}
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GEPVectorIdx[GEP] = Index;
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for (User *GEPUser : AllocaUser->users()) {
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if (!canVectorizeInst(cast<Instruction>(GEPUser), AllocaUser))
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return false;
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WorkList.push_back(GEPUser);
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}
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Users.append(GEP->user_begin(), GEP->user_end());
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UseUsers.append(GEP->getNumUses(), GEP);
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}
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LLVM_DEBUG(dbgs() << " Converting alloca to vector " << *AllocaTy << " -> "
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@ -433,6 +478,8 @@ static bool tryPromoteAllocaToVector(AllocaInst *Alloca) {
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Value *BitCast = Builder.CreateBitCast(Alloca, VecPtrTy);
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Value *VecValue = Builder.CreateLoad(VectorTy, BitCast);
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Value *ExtractElement = Builder.CreateExtractElement(VecValue, Index);
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if (Inst->getType() != VecEltTy)
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ExtractElement = Builder.CreateBitCast(ExtractElement, Inst->getType());
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Inst->replaceAllUsesWith(ExtractElement);
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Inst->eraseFromParent();
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break;
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@ -447,16 +494,14 @@ static bool tryPromoteAllocaToVector(AllocaInst *Alloca) {
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Value *Index = calculateVectorIndex(Ptr, GEPVectorIdx);
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Value *BitCast = Builder.CreateBitCast(Alloca, VecPtrTy);
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Value *VecValue = Builder.CreateLoad(VectorTy, BitCast);
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Value *NewVecValue = Builder.CreateInsertElement(VecValue,
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SI->getValueOperand(),
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Index);
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Value *Elt = SI->getValueOperand();
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if (Elt->getType() != VecEltTy)
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Elt = Builder.CreateBitCast(Elt, VecEltTy);
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Value *NewVecValue = Builder.CreateInsertElement(VecValue, Elt, Index);
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Builder.CreateStore(NewVecValue, BitCast);
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Inst->eraseFromParent();
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break;
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}
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case Instruction::BitCast:
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case Instruction::AddrSpaceCast:
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break;
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default:
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llvm_unreachable("Inconsistency in instructions promotable to vector");
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@ -721,6 +766,7 @@ bool AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I, bool SufficientLDS) {
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if (!I.isStaticAlloca() || I.isArrayAllocation())
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return false;
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const DataLayout &DL = Mod->getDataLayout();
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IRBuilder<> Builder(&I);
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// First try to replace the alloca with a vector
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@ -728,7 +774,7 @@ bool AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I, bool SufficientLDS) {
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LLVM_DEBUG(dbgs() << "Trying to promote " << I << '\n');
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if (tryPromoteAllocaToVector(&I))
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if (tryPromoteAllocaToVector(&I, DL))
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return true; // Promoted to vector.
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if (DisablePromoteAllocaToLDS)
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@ -758,8 +804,6 @@ bool AMDGPUPromoteAlloca::handleAlloca(AllocaInst &I, bool SufficientLDS) {
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const AMDGPUSubtarget &ST = AMDGPUSubtarget::get(*TM, ContainingFunction);
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unsigned WorkGroupSize = ST.getFlatWorkGroupSizes(ContainingFunction).second;
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const DataLayout &DL = Mod->getDataLayout();
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unsigned Align = I.getAlignment();
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if (Align == 0)
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Align = DL.getABITypeAlignment(I.getAllocatedType());
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@ -0,0 +1,352 @@
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-ALLOCA %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-PROMOTE %s
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; RUN: opt -S -mtriple=amdgcn-- -amdgpu-promote-alloca -sroa -instcombine < %s | FileCheck -check-prefix=OPT %s
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target datalayout = "A5"
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; OPT-LABEL: @vector_read_alloca_bitcast(
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; OPT-NOT: alloca
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; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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; OPT-NEXT: store i32 %0, i32 addrspace(1)* %out, align 4
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; GCN-LABEL: {{^}}vector_read_alloca_bitcast:
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; GCN-ALLOCA-COUNT-4: buffer_store_dword
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; GCN-ALLOCA: buffer_load_dword
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; GCN-PROMOTE: v_cmp_eq_u32_e64 [[CC1:[^,]+]], s{{[0-9]+}}, 1
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; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND1:v[0-9]+]], 0, 1, [[CC1]]
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; GCN-PROMOTE: v_cmp_ne_u32_e64 [[CC2:[^,]+]], s{{[0-9]+}}, 2
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; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND2:v[0-9]+]], 2, [[IND1]], [[CC2]]
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; GCN-PROMOTE: v_cmp_ne_u32_e64 [[CC3:[^,]+]], s{{[0-9]+}}, 3
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; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND3:v[0-9]+]], 3, [[IND2]], [[CC3]]
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; GCN-PROMOTE: ScratchSize: 0
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define amdgpu_kernel void @vector_read_alloca_bitcast(i32 addrspace(1)* %out, i32 %index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%x = bitcast [4 x i32] addrspace(5)* %tmp to i32 addrspace(5)*
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 1, i32 addrspace(5)* %y
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store i32 2, i32 addrspace(5)* %z
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store i32 3, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
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%tmp2 = load i32, i32 addrspace(5)* %tmp1
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store i32 %tmp2, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @vector_write_alloca_bitcast(
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; OPT-NOT: alloca
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; OPT: %0 = insertelement <4 x i32> zeroinitializer, i32 1, i32 %w_index
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; OPT-NEXT: %1 = extractelement <4 x i32> %0, i32 %r_index
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; OPT-NEXT: store i32 %1, i32 addrspace(1)* %out, align
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; GCN-LABEL: {{^}}vector_write_alloca_bitcast:
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; GCN-ALLOCA-COUNT-5: buffer_store_dword
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; GCN-ALLOCA: buffer_load_dword
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; GCN-PROMOTE-COUNT-7: v_cndmask
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; GCN-PROMOTE: ScratchSize: 0
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define amdgpu_kernel void @vector_write_alloca_bitcast(i32 addrspace(1)* %out, i32 %w_index, i32 %r_index) {
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entry:
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%tmp = alloca [4 x i32], addrspace(5)
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%x = bitcast [4 x i32] addrspace(5)* %tmp to i32 addrspace(5)*
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%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
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%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
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%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
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store i32 0, i32 addrspace(5)* %x
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store i32 0, i32 addrspace(5)* %y
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store i32 0, i32 addrspace(5)* %z
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store i32 0, i32 addrspace(5)* %w
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%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %w_index
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store i32 1, i32 addrspace(5)* %tmp1
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%tmp2 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %r_index
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%tmp3 = load i32, i32 addrspace(5)* %tmp2
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store i32 %tmp3, i32 addrspace(1)* %out
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ret void
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}
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; OPT-LABEL: @vector_write_read_bitcast_to_float(
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; OPT-NOT: alloca
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; OPT: bb2:
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; OPT: %tmp.sroa.0.0 = phi <6 x float> [ undef, %bb ], [ %0, %bb2 ]
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; OPT: %0 = insertelement <6 x float> %tmp.sroa.0.0, float %tmp73, i32 %tmp10
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; OPT: .preheader:
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; OPT: %bc = bitcast <6 x float> %0 to <6 x i32>
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; OPT: %1 = extractelement <6 x i32> %bc, i32 %tmp20
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; GCN-LABEL: {{^}}vector_write_read_bitcast_to_float:
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; GCN-ALLOCA: buffer_store_dword
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; GCN-PROMOTE-COUNT-6: v_cmp_eq_u16
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; GCN-PROMOTE-COUNT-6: v_cndmask
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; GCN: s_cbranch
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; GCN-ALLOCA: buffer_load_dword
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; GCN-PROMOTE: v_cmp_eq_u16
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; GCN-PROMOTE: v_cndmask
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; GCN-PROMOTE: v_cmp_eq_u16
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; GCN-PROMOTE: v_cndmask
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; GCN-PROMOTE: v_cmp_eq_u16
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; GCN-PROMOTE: v_cndmask
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; GCN-PROMOTE: v_cmp_eq_u16
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; GCN-PROMOTE: v_cndmask
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; GCN-PROMOTE: v_cmp_eq_u16
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; GCN-PROMOTE: v_cndmask
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; GCN-PROMOTE: ScratchSize: 0
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define amdgpu_kernel void @vector_write_read_bitcast_to_float(float addrspace(1)* %arg) {
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bb:
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%tmp = alloca [6 x float], align 4, addrspace(5)
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%tmp1 = bitcast [6 x float] addrspace(5)* %tmp to i8 addrspace(5)*
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call void @llvm.lifetime.start.p5i8(i64 24, i8 addrspace(5)* %tmp1) #2
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br label %bb2
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bb2: ; preds = %bb2, %bb
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%tmp3 = phi i32 [ 0, %bb ], [ %tmp13, %bb2 ]
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp4
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%tmp6 = bitcast float addrspace(1)* %tmp5 to i32 addrspace(1)*
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%tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
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%tmp8 = trunc i32 %tmp3 to i16
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%tmp9 = urem i16 %tmp8, 6
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%tmp10 = zext i16 %tmp9 to i32
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%tmp11 = getelementptr inbounds [6 x float], [6 x float] addrspace(5)* %tmp, i32 0, i32 %tmp10
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%tmp12 = bitcast float addrspace(5)* %tmp11 to i32 addrspace(5)*
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store i32 %tmp7, i32 addrspace(5)* %tmp12, align 4
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%tmp13 = add nuw nsw i32 %tmp3, 1
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%tmp14 = icmp eq i32 %tmp13, 1000
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br i1 %tmp14, label %.preheader, label %bb2
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bb15: ; preds = %.preheader
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call void @llvm.lifetime.end.p5i8(i64 24, i8 addrspace(5)* %tmp1) #2
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ret void
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.preheader: ; preds = %.preheader, %bb2
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%tmp16 = phi i32 [ %tmp27, %.preheader ], [ 0, %bb2 ]
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%tmp17 = trunc i32 %tmp16 to i16
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%tmp18 = urem i16 %tmp17, 6
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%tmp19 = sub nuw nsw i16 5, %tmp18
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%tmp20 = zext i16 %tmp19 to i32
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%tmp21 = getelementptr inbounds [6 x float], [6 x float] addrspace(5)* %tmp, i32 0, i32 %tmp20
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%tmp22 = bitcast float addrspace(5)* %tmp21 to i32 addrspace(5)*
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%tmp23 = load i32, i32 addrspace(5)* %tmp22, align 4
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%tmp24 = zext i32 %tmp16 to i64
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%tmp25 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp24
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%tmp26 = bitcast float addrspace(1)* %tmp25 to i32 addrspace(1)*
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store i32 %tmp23, i32 addrspace(1)* %tmp26, align 4
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%tmp27 = add nuw nsw i32 %tmp16, 1
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%tmp28 = icmp eq i32 %tmp27, 1000
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br i1 %tmp28, label %bb15, label %.preheader
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}
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; OPT-LABEL: @vector_write_read_bitcast_to_double(
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; OPT-NOT: alloca
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; OPT: bb2:
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; OPT: %tmp.sroa.0.0 = phi <6 x double> [ undef, %bb ], [ %0, %bb2 ]
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; OPT: %0 = insertelement <6 x double> %tmp.sroa.0.0, double %tmp73, i32 %tmp10
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; OPT: .preheader:
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; OPT: %bc = bitcast <6 x double> %0 to <6 x i64>
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; OPT: %1 = extractelement <6 x i64> %bc, i32 %tmp20
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; TODO: Fix selection to eliminate scratch
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; GCN-LABEL: {{^}}vector_write_read_bitcast_to_double:
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; GCN-COUNT-2: buffer_store_dword
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; GCN: s_cbranch
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; GCN-COUNT-2: buffer_load_dword
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define amdgpu_kernel void @vector_write_read_bitcast_to_double(double addrspace(1)* %arg) {
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bb:
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%tmp = alloca [6 x double], align 8, addrspace(5)
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%tmp1 = bitcast [6 x double] addrspace(5)* %tmp to i8 addrspace(5)*
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call void @llvm.lifetime.start.p5i8(i64 48, i8 addrspace(5)* %tmp1) #2
|
||||
br label %bb2
|
||||
|
||||
bb2: ; preds = %bb2, %bb
|
||||
%tmp3 = phi i32 [ 0, %bb ], [ %tmp13, %bb2 ]
|
||||
%tmp4 = zext i32 %tmp3 to i64
|
||||
%tmp5 = getelementptr inbounds double, double addrspace(1)* %arg, i64 %tmp4
|
||||
%tmp6 = bitcast double addrspace(1)* %tmp5 to i64 addrspace(1)*
|
||||
%tmp7 = load i64, i64 addrspace(1)* %tmp6, align 8
|
||||
%tmp8 = trunc i32 %tmp3 to i16
|
||||
%tmp9 = urem i16 %tmp8, 6
|
||||
%tmp10 = zext i16 %tmp9 to i32
|
||||
%tmp11 = getelementptr inbounds [6 x double], [6 x double] addrspace(5)* %tmp, i32 0, i32 %tmp10
|
||||
%tmp12 = bitcast double addrspace(5)* %tmp11 to i64 addrspace(5)*
|
||||
store i64 %tmp7, i64 addrspace(5)* %tmp12, align 8
|
||||
%tmp13 = add nuw nsw i32 %tmp3, 1
|
||||
%tmp14 = icmp eq i32 %tmp13, 1000
|
||||
br i1 %tmp14, label %.preheader, label %bb2
|
||||
|
||||
bb15: ; preds = %.preheader
|
||||
call void @llvm.lifetime.end.p5i8(i64 48, i8 addrspace(5)* %tmp1) #2
|
||||
ret void
|
||||
|
||||
.preheader: ; preds = %.preheader, %bb2
|
||||
%tmp16 = phi i32 [ %tmp27, %.preheader ], [ 0, %bb2 ]
|
||||
%tmp17 = trunc i32 %tmp16 to i16
|
||||
%tmp18 = urem i16 %tmp17, 6
|
||||
%tmp19 = sub nuw nsw i16 5, %tmp18
|
||||
%tmp20 = zext i16 %tmp19 to i32
|
||||
%tmp21 = getelementptr inbounds [6 x double], [6 x double] addrspace(5)* %tmp, i32 0, i32 %tmp20
|
||||
%tmp22 = bitcast double addrspace(5)* %tmp21 to i64 addrspace(5)*
|
||||
%tmp23 = load i64, i64 addrspace(5)* %tmp22, align 8
|
||||
%tmp24 = zext i32 %tmp16 to i64
|
||||
%tmp25 = getelementptr inbounds double, double addrspace(1)* %arg, i64 %tmp24
|
||||
%tmp26 = bitcast double addrspace(1)* %tmp25 to i64 addrspace(1)*
|
||||
store i64 %tmp23, i64 addrspace(1)* %tmp26, align 8
|
||||
%tmp27 = add nuw nsw i32 %tmp16, 1
|
||||
%tmp28 = icmp eq i32 %tmp27, 1000
|
||||
br i1 %tmp28, label %bb15, label %.preheader
|
||||
}
|
||||
|
||||
; OPT-LABEL: @vector_write_read_bitcast_to_i64(
|
||||
; OPT-NOT: alloca
|
||||
; OPT: bb2:
|
||||
; OPT: %tmp.sroa.0.0 = phi <6 x i64> [ undef, %bb ], [ %0, %bb2 ]
|
||||
; OPT: %0 = insertelement <6 x i64> %tmp.sroa.0.0, i64 %tmp6, i32 %tmp9
|
||||
; OPT: .preheader:
|
||||
; OPT: %1 = extractelement <6 x i64> %0, i32 %tmp18
|
||||
|
||||
; TODO: Fix selection to eliminate scratch
|
||||
|
||||
; GCN-LABEL: {{^}}vector_write_read_bitcast_to_i64:
|
||||
; GCN-COUNT-2: buffer_store_dword
|
||||
|
||||
; GCN: s_cbranch
|
||||
|
||||
; GCN-COUNT-2: buffer_load_dword
|
||||
|
||||
define amdgpu_kernel void @vector_write_read_bitcast_to_i64(i64 addrspace(1)* %arg) {
|
||||
bb:
|
||||
%tmp = alloca [6 x i64], align 8, addrspace(5)
|
||||
%tmp1 = bitcast [6 x i64] addrspace(5)* %tmp to i8 addrspace(5)*
|
||||
call void @llvm.lifetime.start.p5i8(i64 48, i8 addrspace(5)* %tmp1) #2
|
||||
br label %bb2
|
||||
|
||||
bb2: ; preds = %bb2, %bb
|
||||
%tmp3 = phi i32 [ 0, %bb ], [ %tmp11, %bb2 ]
|
||||
%tmp4 = zext i32 %tmp3 to i64
|
||||
%tmp5 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp4
|
||||
%tmp6 = load i64, i64 addrspace(1)* %tmp5, align 8
|
||||
%tmp7 = trunc i32 %tmp3 to i16
|
||||
%tmp8 = urem i16 %tmp7, 6
|
||||
%tmp9 = zext i16 %tmp8 to i32
|
||||
%tmp10 = getelementptr inbounds [6 x i64], [6 x i64] addrspace(5)* %tmp, i32 0, i32 %tmp9
|
||||
store i64 %tmp6, i64 addrspace(5)* %tmp10, align 8
|
||||
%tmp11 = add nuw nsw i32 %tmp3, 1
|
||||
%tmp12 = icmp eq i32 %tmp11, 1000
|
||||
br i1 %tmp12, label %.preheader, label %bb2
|
||||
|
||||
bb13: ; preds = %.preheader
|
||||
call void @llvm.lifetime.end.p5i8(i64 48, i8 addrspace(5)* %tmp1) #2
|
||||
ret void
|
||||
|
||||
.preheader: ; preds = %.preheader, %bb2
|
||||
%tmp14 = phi i32 [ %tmp23, %.preheader ], [ 0, %bb2 ]
|
||||
%tmp15 = trunc i32 %tmp14 to i16
|
||||
%tmp16 = urem i16 %tmp15, 6
|
||||
%tmp17 = sub nuw nsw i16 5, %tmp16
|
||||
%tmp18 = zext i16 %tmp17 to i32
|
||||
%tmp19 = getelementptr inbounds [6 x i64], [6 x i64] addrspace(5)* %tmp, i32 0, i32 %tmp18
|
||||
%tmp20 = load i64, i64 addrspace(5)* %tmp19, align 8
|
||||
%tmp21 = zext i32 %tmp14 to i64
|
||||
%tmp22 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp21
|
||||
store i64 %tmp20, i64 addrspace(1)* %tmp22, align 8
|
||||
%tmp23 = add nuw nsw i32 %tmp14, 1
|
||||
%tmp24 = icmp eq i32 %tmp23, 1000
|
||||
br i1 %tmp24, label %bb13, label %.preheader
|
||||
}
|
||||
|
||||
; TODO: llvm.assume can be ingored
|
||||
|
||||
; OPT-LABEL: @vector_read_alloca_bitcast_assume(
|
||||
; OPT: %tmp = alloca <4 x i32>, align 16, addrspace(5)
|
||||
; OPT-NEXT: %x = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %tmp, i64 0, i64 0
|
||||
; OPT-NEXT: store i32 0, i32 addrspace(5)* %x, align 16
|
||||
; OPT-NEXT: %0 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp, align 16
|
||||
; OPT-NEXT: %1 = shufflevector <4 x i32> %0, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
|
||||
; OPT-NEXT: store <4 x i32> %1, <4 x i32> addrspace(5)* %tmp, align 16
|
||||
; OPT-NEXT: %2 = extractelement <4 x i32> %1, i32 %index
|
||||
; OPT-NEXT: store i32 %2, i32 addrspace(1)* %out, align 4
|
||||
|
||||
; GCN-LABEL: {{^}}vector_read_alloca_bitcast_assume:
|
||||
; GCN-COUNT-4: buffer_store_dword
|
||||
|
||||
define amdgpu_kernel void @vector_read_alloca_bitcast_assume(i32 addrspace(1)* %out, i32 %index) {
|
||||
entry:
|
||||
%tmp = alloca [4 x i32], addrspace(5)
|
||||
%x = bitcast [4 x i32] addrspace(5)* %tmp to i32 addrspace(5)*
|
||||
%cmp = icmp ne i32 addrspace(5)* %x, null
|
||||
call void @llvm.assume(i1 %cmp)
|
||||
%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
|
||||
%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
|
||||
%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
|
||||
store i32 0, i32 addrspace(5)* %x
|
||||
store i32 1, i32 addrspace(5)* %y
|
||||
store i32 2, i32 addrspace(5)* %z
|
||||
store i32 3, i32 addrspace(5)* %w
|
||||
%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
|
||||
%tmp2 = load i32, i32 addrspace(5)* %tmp1
|
||||
store i32 %tmp2, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; OPT-LABEL: @vector_read_alloca_multiuse(
|
||||
; OPT-NOT: alloca
|
||||
; OPT: %0 = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
|
||||
; OPT-NEXT: %add2 = add nuw nsw i32 %0, 1
|
||||
; OPT-NEXT: store i32 %add2, i32 addrspace(1)* %out, align 4
|
||||
|
||||
; GCN-LABEL: {{^}}vector_read_alloca_multiuse:
|
||||
; GCN-ALLOCA-COUNT-4: buffer_store_dword
|
||||
; GCN-ALLOCA: buffer_load_dword
|
||||
|
||||
; GCN-PROMOTE: v_cmp_eq_u32_e64 [[CC1:[^,]+]], s{{[0-9]+}}, 1
|
||||
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND1:v[0-9]+]], 0, 1, [[CC1]]
|
||||
; GCN-PROMOTE: v_cmp_ne_u32_e64 [[CC2:[^,]+]], s{{[0-9]+}}, 2
|
||||
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND2:v[0-9]+]], 2, [[IND1]], [[CC2]]
|
||||
; GCN-PROMOTE: v_cmp_ne_u32_e64 [[CC3:[^,]+]], s{{[0-9]+}}, 3
|
||||
; GCN-PROMOTE: v_cndmask_b32_e{{32|64}} [[IND3:v[0-9]+]], 3, [[IND2]], [[CC3]]
|
||||
|
||||
; GCN-PROMOTE: ScratchSize: 0
|
||||
|
||||
define amdgpu_kernel void @vector_read_alloca_multiuse(i32 addrspace(1)* %out, i32 %index) {
|
||||
entry:
|
||||
%tmp = alloca [4 x i32], addrspace(5)
|
||||
%b = bitcast [4 x i32] addrspace(5)* %tmp to float addrspace(5)*
|
||||
%x = bitcast float addrspace(5)* %b to i32 addrspace(5)*
|
||||
%y = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 1
|
||||
%z = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 2
|
||||
%w = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 3
|
||||
store i32 0, i32 addrspace(5)* %x
|
||||
store i32 1, i32 addrspace(5)* %y
|
||||
store i32 2, i32 addrspace(5)* %z
|
||||
store i32 3, i32 addrspace(5)* %w
|
||||
%tmp1 = getelementptr [4 x i32], [4 x i32] addrspace(5)* %tmp, i32 0, i32 %index
|
||||
%tmp2 = load i32, i32 addrspace(5)* %tmp1
|
||||
%tmp3 = load i32, i32 addrspace(5)* %x
|
||||
%tmp4 = load i32, i32 addrspace(5)* %y
|
||||
%add1 = add i32 %tmp2, %tmp3
|
||||
%add2 = add i32 %add1, %tmp4
|
||||
store i32 %add2, i32 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.lifetime.start.p5i8(i64 immarg, i8 addrspace(5)* nocapture)
|
||||
|
||||
declare void @llvm.lifetime.end.p5i8(i64 immarg, i8 addrspace(5)* nocapture)
|
||||
|
||||
declare void @llvm.assume(i1)
|
||||
Loading…
Reference in New Issue