forked from OSchip/llvm-project
Add support for FSIN/FCOS when unsafe math ops are enabled. Patch contributed by
Morten Ofstad! llvm-svn: 21632
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@ -24,6 +24,7 @@
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/Statistic.h"
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#include <set>
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@ -64,6 +65,11 @@ namespace {
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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if (!UnsafeFPMath) {
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setOperationAction(ISD::FSIN , MVT::f64 , Expand);
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setOperationAction(ISD::FCOS , MVT::f64 , Expand);
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}
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// These should be promoted to a larger select which is supported.
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/**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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setOperationAction(ISD::SELECT , MVT::i8 , Promote);
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@ -1831,6 +1837,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::FABS:
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case ISD::FNEG:
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case ISD::FSIN:
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case ISD::FCOS:
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case ISD::FSQRT:
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assert(N.getValueType()==MVT::f64 && "Illegal type for this operation");
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Tmp1 = SelectExpr(Node->getOperand(0));
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@ -1839,6 +1847,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::FABS: BuildMI(BB, X86::FABS, 1, Result).addReg(Tmp1); break;
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case ISD::FNEG: BuildMI(BB, X86::FCHS, 1, Result).addReg(Tmp1); break;
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case ISD::FSQRT: BuildMI(BB, X86::FSQRT, 1, Result).addReg(Tmp1); break;
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case ISD::FSIN: BuildMI(BB, X86::FSIN, 1, Result).addReg(Tmp1); break;
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case ISD::FCOS: BuildMI(BB, X86::FCOS, 1, Result).addReg(Tmp1); break;
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}
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return Result;
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