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Handle a wider arrangement of loads. 

llvm-svn: 116284
This commit is contained in:
Eric Christopher 2010-10-12 00:43:21 +00:00
parent f6c73c463f
commit db3bcc9910
1 changed files with 16 additions and 0 deletions
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16
llvm/lib/Target/ARM/ARMFastISel.cpp
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@ -588,6 +588,22 @@ bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
switch (Opcode) {
default:
break;
case Instruction::BitCast: {
// Look through bitcasts.
return ARMComputeRegOffset(U->getOperand(0), Reg, Offset);
}
case Instruction::IntToPtr: {
// Look past no-op inttoptrs.
if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
return ARMComputeRegOffset(U->getOperand(0), Reg, Offset);
break;
}
case Instruction::PtrToInt: {
// Look past no-op ptrtoints.
if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
return ARMComputeRegOffset(U->getOperand(0), Reg, Offset);
break;
}
case Instruction::Alloca: {
// Don't handle dynamic allocas.
assert(!FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Obj)) &&