forked from OSchip/llvm-project
Fill in some missing DL propagation in getNode()s.
llvm-svn: 63595
This commit is contained in:
parent
143a2c3470
commit
db39362c90
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@ -854,8 +854,7 @@ SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
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SDValue NegOneElt =
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getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), EltVT);
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std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
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NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT,
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&NegOnes[0], NegOnes.size());
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NegOne = getNode(ISD::BUILD_VECTOR, DL, VT, &NegOnes[0], NegOnes.size());
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} else {
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NegOne = getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
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}
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@ -2150,10 +2149,11 @@ bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const {
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/// element of the result of the vector shuffle.
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SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
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MVT VT = N->getValueType(0);
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DebugLoc dl = N->getDebugLoc();
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SDValue PermMask = N->getOperand(2);
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SDValue Idx = PermMask.getOperand(i);
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if (Idx.getOpcode() == ISD::UNDEF)
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return getNode(ISD::UNDEF, VT.getVectorElementType());
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return getNode(ISD::UNDEF, dl, VT.getVectorElementType());
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unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
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unsigned NumElems = PermMask.getNumOperands();
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SDValue V = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
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@ -2167,7 +2167,7 @@ SDValue SelectionDAG::getShuffleScalarElt(const SDNode *N, unsigned i) {
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}
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if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
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return (Index == 0) ? V.getOperand(0)
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: getNode(ISD::UNDEF, VT.getVectorElementType());
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: getNode(ISD::UNDEF, dl, VT.getVectorElementType());
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if (V.getOpcode() == ISD::BUILD_VECTOR)
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return V.getOperand(Index);
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if (V.getOpcode() == ISD::VECTOR_SHUFFLE)
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@ -2301,7 +2301,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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Operand.getValueType().isFloatingPoint() && "Invalid FP cast!");
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if (Operand.getValueType() == VT) return Operand; // noop conversion.
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if (Operand.getOpcode() == ISD::UNDEF)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, DL, VT);
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break;
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case ISD::SIGN_EXTEND:
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assert(VT.isInteger() && Operand.getValueType().isInteger() &&
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@ -2310,7 +2310,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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assert(Operand.getValueType().bitsLT(VT)
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&& "Invalid sext node, dst < src!");
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if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
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return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
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return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
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break;
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case ISD::ZERO_EXTEND:
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assert(VT.isInteger() && Operand.getValueType().isInteger() &&
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@ -2319,7 +2319,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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assert(Operand.getValueType().bitsLT(VT)
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&& "Invalid zext node, dst < src!");
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if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x)
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return getNode(ISD::ZERO_EXTEND, VT, Operand.getNode()->getOperand(0));
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return getNode(ISD::ZERO_EXTEND, DL, VT,
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Operand.getNode()->getOperand(0));
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break;
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case ISD::ANY_EXTEND:
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assert(VT.isInteger() && Operand.getValueType().isInteger() &&
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@ -2329,7 +2330,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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&& "Invalid anyext node, dst < src!");
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if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND)
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// (ext (zext x)) -> (zext x) and (ext (sext x)) -> (sext x)
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return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
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return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
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break;
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case ISD::TRUNCATE:
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assert(VT.isInteger() && Operand.getValueType().isInteger() &&
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@ -2338,14 +2339,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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assert(Operand.getValueType().bitsGT(VT)
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&& "Invalid truncate node, src < dst!");
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if (OpOpcode == ISD::TRUNCATE)
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return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0));
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return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
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else if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND ||
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OpOpcode == ISD::ANY_EXTEND) {
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// If the source is smaller than the dest, we still need an extend.
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if (Operand.getNode()->getOperand(0).getValueType().bitsLT(VT))
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return getNode(OpOpcode, VT, Operand.getNode()->getOperand(0));
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return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0));
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else if (Operand.getNode()->getOperand(0).getValueType().bitsGT(VT))
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return getNode(ISD::TRUNCATE, VT, Operand.getNode()->getOperand(0));
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return getNode(ISD::TRUNCATE, DL, VT, Operand.getNode()->getOperand(0));
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else
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return Operand.getNode()->getOperand(0);
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}
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@ -2356,16 +2357,16 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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&& "Cannot BIT_CONVERT between types of different sizes!");
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if (VT == Operand.getValueType()) return Operand; // noop conversion.
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if (OpOpcode == ISD::BIT_CONVERT) // bitconv(bitconv(x)) -> bitconv(x)
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return getNode(ISD::BIT_CONVERT, VT, Operand.getOperand(0));
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return getNode(ISD::BIT_CONVERT, DL, VT, Operand.getOperand(0));
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if (OpOpcode == ISD::UNDEF)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, DL, VT);
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break;
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case ISD::SCALAR_TO_VECTOR:
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assert(VT.isVector() && !Operand.getValueType().isVector() &&
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VT.getVectorElementType() == Operand.getValueType() &&
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"Illegal SCALAR_TO_VECTOR node!");
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if (OpOpcode == ISD::UNDEF)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, DL, VT);
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// scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
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if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
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isa<ConstantSDNode>(Operand.getOperand(1)) &&
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@ -2376,14 +2377,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
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case ISD::FNEG:
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// -(X-Y) -> (Y-X) is unsafe because when X==Y, -0.0 != +0.0
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if (UnsafeFPMath && OpOpcode == ISD::FSUB)
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return getNode(ISD::FSUB, VT, Operand.getNode()->getOperand(1),
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return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
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Operand.getNode()->getOperand(0));
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if (OpOpcode == ISD::FNEG) // --X -> X
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return Operand.getNode()->getOperand(0);
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break;
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case ISD::FABS:
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if (OpOpcode == ISD::FNEG) // abs(-X) -> abs(X)
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return getNode(ISD::FABS, VT, Operand.getNode()->getOperand(0));
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return getNode(ISD::FABS, DL, VT, Operand.getNode()->getOperand(0));
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break;
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}
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@ -2473,7 +2474,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
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N2.getOpcode() == ISD::BUILD_VECTOR) {
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SmallVector<SDValue, 16> Elts(N1.getNode()->op_begin(), N1.getNode()->op_end());
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Elts.insert(Elts.end(), N2.getNode()->op_begin(), N2.getNode()->op_end());
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return getNode(ISD::BUILD_VECTOR, VT, &Elts[0], Elts.size());
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return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size());
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}
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break;
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case ISD::AND:
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@ -2599,7 +2600,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
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case ISD::EXTRACT_VECTOR_ELT:
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// EXTRACT_VECTOR_ELT of an UNDEF is an UNDEF.
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if (N1.getOpcode() == ISD::UNDEF)
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return getNode(ISD::UNDEF, VT);
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return getNode(ISD::UNDEF, DL, VT);
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// EXTRACT_VECTOR_ELT of CONCAT_VECTORS is often formed while lowering is
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// expanding copies of large vectors from registers.
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@ -2608,7 +2609,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
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N1.getNumOperands() > 0) {
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unsigned Factor =
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N1.getOperand(0).getValueType().getVectorNumElements();
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return getNode(ISD::EXTRACT_VECTOR_ELT, VT,
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return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
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N1.getOperand(N2C->getZExtValue() / Factor),
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getConstant(N2C->getZExtValue() % Factor,
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N2.getValueType()));
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@ -2629,7 +2630,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
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// the original vector.
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else if (isa<ConstantSDNode>(N1.getOperand(2)) &&
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isa<ConstantSDNode>(N2))
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return getNode(ISD::EXTRACT_VECTOR_ELT, VT, N1.getOperand(0), N2);
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return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), N2);
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}
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break;
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case ISD::EXTRACT_ELEMENT:
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@ -2990,7 +2991,8 @@ static SDValue getMemsetStringVal(MVT VT, SelectionDAG &DAG,
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static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
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SelectionDAG &DAG) {
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MVT VT = Base.getValueType();
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return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
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return DAG.getNode(ISD::ADD, Base.getNode()->getDebugLoc(),
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VT, Base, DAG.getConstant(Offset, VT));
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}
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/// isMemSrcFromString - Returns true if memcpy source is a string constant.
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@ -4932,7 +4934,7 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
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MVT VT1, MVT VT2, MVT VT3,
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const SDValue *Ops, unsigned NumOps) {
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const MVT *VTs = getNodeValueTypes(VT1, VT2, VT3);
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return getNode(~Opcode, VTs, 3, Ops, NumOps).getNode();
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return getNode(~Opcode, dl, VTs, 3, Ops, NumOps).getNode();
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}
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SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT VT1,
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