forked from OSchip/llvm-project
One more coalescer fix wrt deadness propagation.
llvm-svn: 48837
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289ba4f335
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@ -554,6 +554,23 @@ void SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
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}
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}
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/// PropagateDeadness - Propagate the dead marker to the instruction which
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/// defines the val#.
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static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
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unsigned &LRStart, LiveIntervals *li_,
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const TargetRegisterInfo* tri_) {
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MachineInstr *DefMI =
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li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
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if (DefMI && DefMI != CopyMI) {
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int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
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if (DeadIdx != -1) {
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DefMI->getOperand(DeadIdx).setIsDead();
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// A dead def should have a single cycle interval.
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++LRStart;
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}
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}
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}
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/// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
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/// extended by a dead copy. Mark the last use (if any) of the val# as kill
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/// as ends the live range there. If there isn't another use, then this
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@ -613,23 +630,14 @@ SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
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// Live-in to the function but dead. Remove it from entry live-in set.
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mf_->begin()->removeLiveIn(li.reg);
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}
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removeRange(li, LR->start, LR->end, li_, tri_);
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// FIXME: Shorten intervals in BBs that reaches this BB.
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} else {
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// Not livein into BB.
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MachineInstr *DefMI =
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li_->getInstructionFromIndex(li_->getDefIndex(RemoveStart));
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if (DefMI && DefMI != CopyMI) {
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int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
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if (DeadIdx != -1) {
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DefMI->getOperand(DeadIdx).setIsDead();
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// A dead def should have a single cycle interval.
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++RemoveStart;
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}
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}
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removeRange(li, RemoveStart, LR->end, li_, tri_);
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}
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if (LR->valno->def == RemoveStart)
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// If the def MI defines the val#, propagate the dead marker.
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PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
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removeRange(li, RemoveStart, LR->end, li_, tri_);
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removeIntervalIfEmpty(li, li_, tri_);
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}
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@ -0,0 +1,28 @@
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; RUN: llvm-as < %s | llc -mtriple=powerpc-apple-darwin
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define i32 @t(i64 %byteStart, i32 %activeIndex) nounwind {
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entry:
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%tmp50 = load i32* null, align 4 ; <i32> [#uses=1]
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%tmp5051 = zext i32 %tmp50 to i64 ; <i64> [#uses=3]
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%tmp53 = udiv i64 %byteStart, %tmp5051 ; <i64> [#uses=1]
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%tmp5354 = trunc i64 %tmp53 to i32 ; <i32> [#uses=1]
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%tmp62 = urem i64 %byteStart, %tmp5051 ; <i64> [#uses=1]
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%tmp94 = add i32 0, 1 ; <i32> [#uses=1]
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%tmp100 = urem i32 %tmp94, 0 ; <i32> [#uses=2]
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%tmp108 = add i32 0, %activeIndex ; <i32> [#uses=1]
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%tmp110 = sub i32 %tmp108, 0 ; <i32> [#uses=1]
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%tmp112 = urem i32 %tmp110, 0 ; <i32> [#uses=2]
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%tmp122 = icmp ult i32 %tmp112, %tmp100 ; <i1> [#uses=1]
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%iftmp.175.0 = select i1 %tmp122, i32 %tmp112, i32 %tmp100 ; <i32> [#uses=1]
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%tmp119 = add i32 %tmp5354, 0 ; <i32> [#uses=1]
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%tmp131 = add i32 %tmp119, %iftmp.175.0 ; <i32> [#uses=1]
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%tmp131132 = zext i32 %tmp131 to i64 ; <i64> [#uses=1]
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%tmp147 = mul i64 %tmp131132, %tmp5051 ; <i64> [#uses=1]
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br i1 false, label %bb164, label %bb190
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bb164: ; preds = %entry
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%tmp171172 = and i64 %tmp62, 4294967295 ; <i64> [#uses=1]
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%tmp173 = add i64 %tmp171172, %tmp147 ; <i64> [#uses=0]
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ret i32 0
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bb190: ; preds = %entry
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ret i32 0
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}
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