From db37937a4738f3a697804d8b2244baec076867a2 Mon Sep 17 00:00:00 2001
From: Meera Nakrani <meera.nakrani@arm.com>
Date: Fri, 24 Jul 2020 17:46:25 +0000
Subject: [PATCH] [ARM] Added additional patterns to VABD instruction

Added extra patterns to VABD instruction so it is selected in place of VSUB and VABS. Added corresponding regression test too.

Differential Revision: https://reviews.llvm.org/D84500
---
 llvm/lib/Target/ARM/ARMInstrMVE.td   |  7 ++++
 llvm/test/CodeGen/Thumb2/mve-vabd.ll | 63 ++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+)
 create mode 100644 llvm/test/CodeGen/Thumb2/mve-vabd.ll

diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index fa04a82b0ee2..b082ca4d1c90 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -3775,6 +3775,13 @@ multiclass MVE_VABD_fp_m<MVEVectorVTInfo VTI>
 defm MVE_VABDf32 : MVE_VABD_fp_m<MVE_v4f32>;
 defm MVE_VABDf16 : MVE_VABD_fp_m<MVE_v8f16>; 
 
+let Predicates = [HasMVEFloat] in {
+  def : Pat<(v8f16 (fabs (fsub (v8f16 MQPR:$Qm), (v8f16 MQPR:$Qn)))),
+        (MVE_VABDf16 MQPR:$Qm, MQPR:$Qn)>;
+  def : Pat<(v4f32 (fabs (fsub (v4f32 MQPR:$Qm), (v4f32 MQPR:$Qn)))),
+        (MVE_VABDf32 MQPR:$Qm, MQPR:$Qn)>;
+}
+
 class MVE_VCVT_fix<string suffix, bit fsi, bit U, bit op,
                    Operand imm_operand_type>
   : MVE_float<"vcvt", suffix,
diff --git a/llvm/test/CodeGen/Thumb2/mve-vabd.ll b/llvm/test/CodeGen/Thumb2/mve-vabd.ll
new file mode 100644
index 000000000000..3bbf2fc23a1c
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/mve-vabd.ll
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve %s -o - | FileCheck %s  --check-prefix=CHECK --check-prefix=CHECK-MVE
+; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
+
+define arm_aapcs_vfpcc void @vabd_v4f32(<4 x float> %x, <4 x float> %y, <4 x float>* %z) {
+; CHECK-MVE-LABEL: vabd_v4f32
+; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:  .save {r4, r5, r6, r7, lr}
+; CHECK-MVE-NEXT:  push {r4, r5, r6, r7, lr}
+; CHECK-MVE-NEXT:  .pad #4
+; CHECK-MVE-NEXT:  sub sp, #4
+; CHECK-MVE-NEXT:  .vsave {d8, d9, d10, d11}
+; CHECK-MVE-NEXT:  vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT:  vmov q4, q1
+; CHECK-MVE-NEXT:  vmov q5, q0
+; CHECK-MVE-NEXT:  mov r4, r0
+; CHECK-MVE-NEXT:  vmov r0, s20
+; CHECK-MVE-NEXT:  vmov r1, s16
+; CHECK-MVE-NEXT:  bl __aeabi_fsub
+; CHECK-MVE-NEXT:  mov r5, r0
+; CHECK-MVE-NEXT:  vmov r0, s21
+
+; CHECK-MVEFP-LABEL: vabd_v4f32
+; CHECK-MVEFP:       @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT:  vabd.f32 q0, q0, q1
+; CHECK-MVEFP-NEXT:  vstrw.32 q0, [r0]
+; CHECK-MVEFP-NEXT:  bx lr
+entry:
+  %0 = fsub <4 x float> %x, %y
+  %1 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %0)
+  store <4 x float> %1, <4 x float>* %z, align 4
+  ret void
+}
+
+define arm_aapcs_vfpcc void @vabd_v8f16(<8 x half> %x, <8 x half> %y, <8 x half>* %z) {
+; CHECK-MVE-LABEL: vabd_v8f16
+; CHECK-MVE:       @ %bb.0: @ %entry
+; CHECK-MVE-NEXT:  .save {r4, r5, r6, lr}
+; CHECK-MVE-NEXT:  push {r4, r5, r6, lr}
+; CHECK-MVE-NEXT:  .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-MVE-NEXT:  vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-MVE-NEXT:  mov r4, r0
+; CHECK-MVE-NEXT:  vmov.u16 r0, q1[1]
+; CHECK-MVE-NEXT:  vmov q5, q1
+; CHECK-MVE-NEXT:  vmov q4, q0
+; CHECK-MVE-NEXT:   bl __aeabi_h2f
+; CHECK-MVE-NEXT:  mov r5, r0
+; CHECK-MVE-NEXT:  vmov.u16 r0, q4[1]
+
+; CHECK-MVEFP-LABEL: vabd_v8f16
+; CHECK-MVEFP:       @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT:  vabd.f16 q0, q0, q1
+; CHECK-MVEFP-NEXT:  vstrw.32 q0, [r0]
+; CHECK-MVEFP-NEXT:  bx lr
+entry:
+  %0 = fsub <8 x half> %x, %y
+  %1 = call <8 x half> @llvm.fabs.v8f16(<8 x half> %0)
+  store <8 x half> %1, <8 x half>* %z
+  ret void
+}
+
+declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
+declare <8 x half> @llvm.fabs.v8f16(<8 x half>)