forked from OSchip/llvm-project
parent
e450358a21
commit
db2ccdcfd2
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@ -766,8 +766,8 @@ MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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// loopMBB:
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// ll oldval, 0(ptr)
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// <binop> tmp1, oldval, incr
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// sc tmp1, 0(ptr)
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// beq tmp1, $0, loopMBB
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// sc tmp3, tmp1, 0(ptr)
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// beq tmp3, $0, loopMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Ptr).addImm(0);
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if (Nand) {
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@ -877,8 +877,8 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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// and newval,tmp7,mask
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// and tmp8,oldval,mask2
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// or tmp9,tmp8,newval
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// sc tmp9,0(addr)
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// beq tmp9,$0,loopMBB
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// sc tmp13,tmp9,0(addr)
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// beq tmp13,$0,loopMBB
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// atomic.swap
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// loopMBB:
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@ -886,8 +886,8 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
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// and newval,incr2,mask
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// and tmp8,oldval,mask2
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// or tmp9,tmp8,newval
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// sc tmp9,0(addr)
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// beq tmp9,$0,loopMBB
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// sc tmp13,tmp9,0(addr)
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// beq tmp13,$0,loopMBB
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BB = loopMBB;
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BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addReg(Addr).addImm(0);
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@ -988,8 +988,8 @@ MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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.addReg(Dest).addReg(Oldval).addMBB(exitMBB);
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// loop2MBB:
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// sc tmp1, 0(ptr)
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// beq tmp1, $0, loop1MBB
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// sc tmp3, tmp1, 0(ptr)
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// beq tmp3, $0, loop1MBB
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BB = loop2MBB;
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BuildMI(BB, dl, TII->get(Mips::SC), Tmp3).addReg(Newval).addReg(Ptr).addImm(0);
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BuildMI(BB, dl, TII->get(Mips::BEQ))
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@ -1102,8 +1102,8 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
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// loop2MBB:
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// and tmp6,oldval3,mask2
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// or tmp7,tmp6,newval2
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// sc tmp7,0(addr)
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// beq tmp7,$0,loop1MBB
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// sc tmp10,tmp7,0(addr)
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// beq tmp10,$0,loop1MBB
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BB = loop2MBB;
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BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2);
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BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2);
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