forked from OSchip/llvm-project
RISCV: Avoid GlobalISel build break in a future patch
The GlobalISelEmitter is stricter about matching timm instruction outputs to timm inputs (although in an accidental sort of way that doesn't hit a proper import failure error). Also, apparently no intrinsic patterns were importing since the ID enum declaration was missing.
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@ -235,13 +235,13 @@ class PseudoMaskedAMOUMinUMax
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class PseudoMaskedAMOPat<Intrinsic intrin, Pseudo AMOInst>
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: Pat<(intrin GPR:$addr, GPR:$incr, GPR:$mask, timm:$ordering),
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(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, imm:$ordering)>;
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(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, timm:$ordering)>;
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class PseudoMaskedAMOMinMaxPat<Intrinsic intrin, Pseudo AMOInst>
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: Pat<(intrin GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
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timm:$ordering),
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(AMOInst GPR:$addr, GPR:$incr, GPR:$mask, GPR:$shiftamt,
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imm:$ordering)>;
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timm:$ordering)>;
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def PseudoMaskedAtomicSwap32 : PseudoMaskedAMO;
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def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_xchg_i32,
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@ -310,7 +310,7 @@ def PseudoMaskedCmpXchg32
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def : Pat<(int_riscv_masked_cmpxchg_i32
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GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
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(PseudoMaskedCmpXchg32
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GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, imm:$ordering)>;
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GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
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} // Predicates = [HasStdExtA]
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@ -387,5 +387,5 @@ defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64>;
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def : Pat<(int_riscv_masked_cmpxchg_i64
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GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),
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(PseudoMaskedCmpXchg32
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GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, imm:$ordering)>;
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GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering)>;
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} // Predicates = [HasStdExtA, IsRV64]
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@ -16,6 +16,7 @@
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#include "RISCVTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
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#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
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#include "llvm/IR/IntrinsicsRISCV.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "riscv-isel"
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