forked from OSchip/llvm-project
[mips] Add support for Global INValidate ASE
This includes Instructions: ginvi, ginvt, Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv Attribute: ginv .MIPS.abiflags: GINV (0x20000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D46268 llvm-svn: 332624
This commit is contained in:
Petar Jovanovic
parent
bd332588bd
commit
daf5169398
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@ -43,7 +43,8 @@ enum AFL_ASE {
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AFL_ASE_MIPS16 = 0x00000400, // MIPS16 ASE
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AFL_ASE_MICROMIPS = 0x00000800, // MICROMIPS ASE
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AFL_ASE_XPA = 0x00001000, // XPA ASE
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AFL_ASE_CRC = 0x00008000 // CRC ASE
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AFL_ASE_CRC = 0x00008000, // CRC ASE
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AFL_ASE_GINV = 0x00020000 // GINV ASE
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};
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// Values for the isa_ext word of an ABI flags structure.
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@ -350,6 +350,7 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool parseSetNoMtDirective();
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bool parseSetNoCRCDirective();
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bool parseSetNoVirtDirective();
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bool parseSetNoGINVDirective();
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bool parseSetAssignment();
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@ -654,6 +655,10 @@ public:
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return getSTI().getFeatureBits()[Mips::FeatureVirt];
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}
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bool hasGINV() const {
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return getSTI().getFeatureBits()[Mips::FeatureGINV];
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}
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/// Warn if RegIndex is the same as the current AT.
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void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);
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@ -6740,6 +6745,23 @@ bool MipsAsmParser::parseSetNoVirtDirective() {
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return false;
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}
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bool MipsAsmParser::parseSetNoGINVDirective() {
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MCAsmParser &Parser = getParser();
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Parser.Lex(); // Eat "noginv".
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// If this is not the end of the statement, report an error.
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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reportParseError("unexpected token, expected end of statement");
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return false;
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}
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clearFeatureBits(Mips::FeatureGINV, "ginv");
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getTargetStreamer().emitDirectiveSetNoGINV();
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Parser.Lex(); // Consume the EndOfStatement.
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return false;
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}
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bool MipsAsmParser::parseSetPopDirective() {
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MCAsmParser &Parser = getParser();
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SMLoc Loc = getLexer().getLoc();
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@ -6969,6 +6991,10 @@ bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
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setFeatureBits(Mips::FeatureVirt, "virt");
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getTargetStreamer().emitDirectiveSetVirt();
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break;
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case Mips::FeatureGINV:
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setFeatureBits(Mips::FeatureGINV, "ginv");
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getTargetStreamer().emitDirectiveSetGINV();
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break;
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}
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return false;
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}
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@ -7281,6 +7307,10 @@ bool MipsAsmParser::parseDirectiveSet() {
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return parseSetFeature(Mips::FeatureVirt);
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} else if (Tok.getString() == "novirt") {
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return parseSetNoVirtDirective();
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} else if (Tok.getString() == "ginv") {
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return parseSetFeature(Mips::FeatureGINV);
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} else if (Tok.getString() == "noginv") {
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return parseSetNoGINVDirective();
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} else {
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// It is just an identifier, look for an assignment.
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parseSetAssignment();
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@ -7531,6 +7561,8 @@ bool MipsAsmParser::parseSSectionDirective(StringRef Section, unsigned Type) {
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/// ::= .module nocrc
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/// ::= .module virt
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/// ::= .module novirt
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/// ::= .module ginv
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/// ::= .module noginv
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bool MipsAsmParser::parseDirectiveModule() {
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MCAsmParser &Parser = getParser();
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MCAsmLexer &Lexer = getLexer();
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@ -7724,6 +7756,44 @@ bool MipsAsmParser::parseDirectiveModule() {
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return false;
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}
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return false; // parseDirectiveModule has finished successfully.
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} else if (Option == "ginv") {
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setModuleFeatureBits(Mips::FeatureGINV, "ginv");
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// Synchronize the ABI Flags information with the FeatureBits information we
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// updated above.
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getTargetStreamer().updateABIInfo(*this);
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// If printing assembly, use the recently updated ABI Flags information.
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// If generating ELF, don't do anything (the .MIPS.abiflags section gets
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// emitted later).
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getTargetStreamer().emitDirectiveModuleGINV();
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// If this is not the end of the statement, report an error.
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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reportParseError("unexpected token, expected end of statement");
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return false;
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}
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return false; // parseDirectiveModule has finished successfully.
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} else if (Option == "noginv") {
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clearModuleFeatureBits(Mips::FeatureGINV, "ginv");
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// Synchronize the ABI Flags information with the FeatureBits information we
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// updated above.
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getTargetStreamer().updateABIInfo(*this);
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// If printing assembly, use the recently updated ABI Flags information.
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// If generating ELF, don't do anything (the .MIPS.abiflags section gets
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// emitted later).
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getTargetStreamer().emitDirectiveModuleNoGINV();
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// If this is not the end of the statement, report an error.
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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reportParseError("unexpected token, expected end of statement");
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return false;
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}
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return false; // parseDirectiveModule has finished successfully.
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} else {
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return Error(L, "'" + Twine(Option) + "' is not a valid .module option.");
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@ -165,6 +165,8 @@ public:
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ASESet |= Mips::AFL_ASE_CRC;
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if (P.hasVirt())
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ASESet |= Mips::AFL_ASE_VIRT;
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if (P.hasGINV())
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ASESet |= Mips::AFL_ASE_GINV;
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}
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template <class PredicateLibrary>
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@ -56,6 +56,8 @@ void MipsTargetStreamer::emitDirectiveSetCRC() {}
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void MipsTargetStreamer::emitDirectiveSetNoCRC() {}
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void MipsTargetStreamer::emitDirectiveSetVirt() {}
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void MipsTargetStreamer::emitDirectiveSetNoVirt() {}
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void MipsTargetStreamer::emitDirectiveSetGINV() {}
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void MipsTargetStreamer::emitDirectiveSetNoGINV() {}
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void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
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forbidModuleDirective();
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@ -130,6 +132,8 @@ void MipsTargetStreamer::emitDirectiveModuleCRC() {}
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void MipsTargetStreamer::emitDirectiveModuleNoCRC() {}
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void MipsTargetStreamer::emitDirectiveModuleVirt() {}
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void MipsTargetStreamer::emitDirectiveModuleNoVirt() {}
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void MipsTargetStreamer::emitDirectiveModuleGINV() {}
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void MipsTargetStreamer::emitDirectiveModuleNoGINV() {}
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void MipsTargetStreamer::emitDirectiveSetFp(
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MipsABIFlagsSection::FpABIKind Value) {
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forbidModuleDirective();
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@ -449,6 +453,16 @@ void MipsTargetAsmStreamer::emitDirectiveSetNoVirt() {
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MipsTargetStreamer::emitDirectiveSetNoVirt();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetGINV() {
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OS << "\t.set\tginv\n";
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MipsTargetStreamer::emitDirectiveSetGINV();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoGINV() {
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OS << "\t.set\tnoginv\n";
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MipsTargetStreamer::emitDirectiveSetNoGINV();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetAt() {
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OS << "\t.set\tat\n";
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MipsTargetStreamer::emitDirectiveSetAt();
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@ -738,6 +752,14 @@ void MipsTargetAsmStreamer::emitDirectiveModuleNoVirt() {
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OS << "\t.module\tnovirt\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveModuleGINV() {
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OS << "\t.module\tginv\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveModuleNoGINV() {
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OS << "\t.module\tnoginv\n";
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}
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// This part is for ELF object output.
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MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
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const MCSubtargetInfo &STI)
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@ -889,6 +889,23 @@ class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
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let Inst{5-0} = opcode;
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}
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class POOL32A_GINV_FM_MMR6<string instr_asm, bits<2> ginv>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> rs;
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bits<2> type;
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bits<32> Inst;
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let Inst{31-26} = 0x0;
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let Inst{25-21} = 0x0;
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let Inst{20-16} = rs;
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let Inst{15-13} = 0b011;
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let Inst{12-11} = ginv;
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let Inst{10-9} = type;
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let Inst{8-6} = 0b101;
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let Inst{5-0} = 0b111100;
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}
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class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
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: MMR6Arch<instr_asm> {
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bits<5> rt;
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@ -106,6 +106,8 @@ class DI_MMR6_ENC : POOL32A_EIDI_MMR6_ENC<"di", 0b0100011101>;
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class ERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0x3cd>;
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class DERET_MMR6_ENC : POOL32A_ERET_FM_MMR6<"eret", 0b1110001101>;
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class ERETNC_MMR6_ENC : ERETNC_FM_MMR6<"eretnc">;
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class GINVI_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvi", 0b00>;
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class GINVT_MMR6_ENC : POOL32A_GINV_FM_MMR6<"ginvt", 0b10>;
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class JALRC16_MMR6_ENC : POOL16C_JALRC_FM_MM16R6<0xb>;
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class JIALC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b100000>;
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class JIC_MMR6_ENC : JMP_IDX_COMPACT_FM<0b101000>;
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@ -826,6 +828,25 @@ class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> {
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class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>;
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class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>;
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class GINV_MMR6_DESC_BASE<string opstr,
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RegisterOperand SrcRC, InstrItinClass Itin> {
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dag InOperandList = (ins SrcRC:$rs, uimm2:$type);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(opstr, "\t$rs, $type");
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list<dag> Pattern = [];
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Format f = FrmFR;
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string BaseOpcode = opstr;
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InstrItinClass Itinerary = Itin;
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}
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class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
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II_GINVI> {
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dag InOperandList = (ins GPR32Opnd:$rs);
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string AsmString = "ginvi\t$rs";
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}
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class GINVT_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvt", GPR32Opnd,
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II_GINVT>;
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/// Floating Point Instructions
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class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
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InstrItinClass Itin, bit isComm,
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@ -1346,6 +1367,10 @@ def ERET_MMR6 : StdMMR6Rel, ERET_MMR6_DESC, ERET_MMR6_ENC, ISA_MICROMIPS32R6;
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def DERET_MMR6 : StdMMR6Rel, DERET_MMR6_DESC, DERET_MMR6_ENC, ISA_MICROMIPS32R6;
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def ERETNC_MMR6 : R6MMR6Rel, ERETNC_MMR6_DESC, ERETNC_MMR6_ENC,
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ISA_MICROMIPS32R6;
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def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_ENC, GINVI_MMR6_DESC,
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ISA_MICROMIPS32R6, ASE_GINV;
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def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
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ISA_MICROMIPS32R6, ASE_GINV;
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def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
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ISA_MICROMIPS32R6;
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def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
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@ -182,6 +182,9 @@ def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Mips R6 CRC ASE">;
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def FeatureVirt : SubtargetFeature<"virt", "HasVirt", "true",
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"Mips Virtualization ASE">;
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def FeatureGINV : SubtargetFeature<"ginv", "HasGINV", "true",
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"Mips Global Invalidate ASE">;
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def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
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"microMips mode">;
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@ -591,3 +591,15 @@ class SPECIAL3_2R_SZ_CRC<bits<2> sz, bits<3> direction> : MipsR6Inst {
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string DecoderMethod = "DecodeCRC";
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}
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class SPECIAL3_GINV<bits<2> ginv> : MipsR6Inst {
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bits<5> rs;
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bits<2> type_;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = rs;
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let Inst{20-10} = 0x0;
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let Inst{9-8} = type_;
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let Inst{7-6} = ginv;
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let Inst{5-0} = 0b111101;
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}
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@ -197,6 +197,9 @@ class CRC32CB_ENC : SPECIAL3_2R_SZ_CRC<0,1>;
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class CRC32CH_ENC : SPECIAL3_2R_SZ_CRC<1,1>;
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class CRC32CW_ENC : SPECIAL3_2R_SZ_CRC<2,1>;
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class GINVI_ENC : SPECIAL3_GINV<0>;
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class GINVT_ENC : SPECIAL3_GINV<2>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Multiclasses
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@ -827,6 +830,22 @@ class CRC32CB_DESC : CRC_DESC_BASE<"crc32cb", GPR32Opnd, II_CRC32CB>;
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class CRC32CH_DESC : CRC_DESC_BASE<"crc32ch", GPR32Opnd, II_CRC32CH>;
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class CRC32CW_DESC : CRC_DESC_BASE<"crc32cw", GPR32Opnd, II_CRC32CW>;
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class GINV_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
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InstrItinClass itin> : MipsR6Arch<instr_asm> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins GPROpnd:$rs, uimm2:$type_);
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string AsmString = !strconcat(instr_asm, "\t$rs, $type_");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = itin;
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bit hasSideEffects = 1;
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}
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class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
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dag InOperandList = (ins GPR32Opnd:$rs);
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string AsmString = "ginvi\t$rs";
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}
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class GINVT_DESC : GINV_DESC_BASE<"ginvt", GPR32Opnd, II_GINVT>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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@ -955,6 +974,11 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def CRC32CW : R6MMR6Rel, CRC32CW_ENC, CRC32CW_DESC, ISA_MIPS32R6, ASE_CRC;
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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def GINVI : R6MMR6Rel, GINVI_ENC, GINVI_DESC, ISA_MIPS32R6, ASE_GINV;
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def GINVT : R6MMR6Rel, GINVT_ENC, GINVT_DESC, ISA_MIPS32R6, ASE_GINV;
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Aliases
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@ -252,6 +252,8 @@ def HasCRC : Predicate<"Subtarget->hasCRC()">,
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AssemblerPredicate<"FeatureCRC">;
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def HasVirt : Predicate<"Subtarget->hasVirt()">,
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AssemblerPredicate<"FeatureVirt">;
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def HasGINV : Predicate<"Subtarget->hasGINV()">,
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AssemblerPredicate<"FeatureGINV">;
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// TODO: Add support for FPOpFusion::Standard
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def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion =="
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" FPOpFusion::Fast">;
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@ -468,6 +470,10 @@ class ASE_VIRT {
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list <Predicate> ASEPredicate = [HasVirt];
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}
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class ASE_GINV {
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list <Predicate> ASEPredicate = [HasGINV];
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}
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// Class used for separating microMIPSr6 and microMIPS (r3) instruction.
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// It can be used only on instructions that doesn't inherit PredicateControl.
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class ISA_MICROMIPS_NOT_32R6 : PredicateControl {
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@ -130,6 +130,8 @@ def II_EVPE : InstrItinClass;
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def II_EXT : InstrItinClass; // Any EXT instruction
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def II_FLOOR : InstrItinClass;
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def II_FORK : InstrItinClass;
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def II_GINVI : InstrItinClass;
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def II_GINVT : InstrItinClass;
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def II_HYPCALL : InstrItinClass;
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def II_INS : InstrItinClass; // Any INS instruction
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def II_IndirectBranchPseudo : InstrItinClass; // Indirect branch pseudo.
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@ -728,5 +730,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
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InstrItinData<II_TLBWI , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_TLBWR , [InstrStage<2, [ALU]>]>,
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InstrItinData<II_DMFGC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_DMTGC0 , [InstrStage<2, [ALU]>]>
|
||||
InstrItinData<II_DMTGC0 , [InstrStage<2, [ALU]>]>,
|
||||
InstrItinData<II_GINVI , [InstrStage<1, [ALU]>]>,
|
||||
InstrItinData<II_GINVT , [InstrStage<1, [ALU]>]>
|
||||
]>;
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
|
|||
HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
|
||||
Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
|
||||
HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
|
||||
HasVirt(false), UseIndirectJumpsHazard(false),
|
||||
HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
|
||||
StackAlignOverride(StackAlignOverride),
|
||||
TM(TM), TargetTriple(TT), TSInfo(),
|
||||
InstrInfo(
|
||||
|
|
|
|||
|
|
@ -168,6 +168,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
|
|||
// HasVirt -- supports Virtualization ASE
|
||||
bool HasVirt;
|
||||
|
||||
// HasGINV -- supports R6 Global INValidate ASE
|
||||
bool HasGINV;
|
||||
|
||||
// Use hazard variants of the jump register instructions for indirect
|
||||
// function calls and jump tables.
|
||||
bool UseIndirectJumpsHazard;
|
||||
|
|
@ -294,6 +297,7 @@ public:
|
|||
bool hasMT() const { return HasMT; }
|
||||
bool hasCRC() const { return HasCRC; }
|
||||
bool hasVirt() const { return HasVirt; }
|
||||
bool hasGINV() const { return HasGINV; }
|
||||
bool useIndirectJumpsHazard() const {
|
||||
return UseIndirectJumpsHazard && hasMips32r2();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -46,6 +46,8 @@ public:
|
|||
virtual void emitDirectiveSetNoCRC();
|
||||
virtual void emitDirectiveSetVirt();
|
||||
virtual void emitDirectiveSetNoVirt();
|
||||
virtual void emitDirectiveSetGINV();
|
||||
virtual void emitDirectiveSetNoGINV();
|
||||
virtual void emitDirectiveSetAt();
|
||||
virtual void emitDirectiveSetAtWithArg(unsigned RegNo);
|
||||
virtual void emitDirectiveSetNoAt();
|
||||
|
|
@ -111,6 +113,8 @@ public:
|
|||
virtual void emitDirectiveModuleNoCRC();
|
||||
virtual void emitDirectiveModuleVirt();
|
||||
virtual void emitDirectiveModuleNoVirt();
|
||||
virtual void emitDirectiveModuleGINV();
|
||||
virtual void emitDirectiveModuleNoGINV();
|
||||
|
||||
void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
|
||||
const MCSubtargetInfo *STI);
|
||||
|
|
@ -225,6 +229,8 @@ public:
|
|||
void emitDirectiveSetNoCRC() override;
|
||||
void emitDirectiveSetVirt() override;
|
||||
void emitDirectiveSetNoVirt() override;
|
||||
void emitDirectiveSetGINV() override;
|
||||
void emitDirectiveSetNoGINV() override;
|
||||
void emitDirectiveSetAt() override;
|
||||
void emitDirectiveSetAtWithArg(unsigned RegNo) override;
|
||||
void emitDirectiveSetNoAt() override;
|
||||
|
|
@ -294,6 +300,8 @@ public:
|
|||
void emitDirectiveModuleNoCRC() override;
|
||||
void emitDirectiveModuleVirt() override;
|
||||
void emitDirectiveModuleNoVirt() override;
|
||||
void emitDirectiveModuleGINV() override;
|
||||
void emitDirectiveModuleNoGINV() override;
|
||||
void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value) override;
|
||||
void emitDirectiveSetOddSPReg() override;
|
||||
void emitDirectiveSetNoOddSPReg() override;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
|
||||
# RUN: -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
|
||||
|
||||
0x3d 0x02 0x40 0x7c # CHECK: ginvi $2
|
||||
0xbd 0x02 0x40 0x7c # CHECK: ginvt $2, 2
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
|
||||
# RUN: -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
|
||||
|
||||
0x02 0x00 0x7c 0x65 # CHECK: ginvi $2
|
||||
0x02 0x00 0x7c 0x75 # CHECK: ginvt $2, 2
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
|
||||
# RUN: -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
|
||||
|
||||
0x00 0x02 0x65 0x7c # CHECK: ginvi $2
|
||||
0x00 0x02 0x75 0x7c # CHECK: ginvt $2, 2
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
|
||||
# RUN: -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
|
||||
|
||||
0x7c 0x40 0x02 0x3d # CHECK: ginvi $2
|
||||
0x7c 0x40 0x02 0xbd # CHECK: ginvt $2, 2
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
# Instructions that are invalid.
|
||||
#
|
||||
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+ginv 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 -mattr=+ginv 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 \
|
||||
# RUN: -mattr=+micromips,+ginv 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
ginvi # CHECK: :[[@LINE]]:3: error: too few operands for instruction
|
||||
ginvi 0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
|
||||
ginvi $4, 0 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
|
||||
ginvi $4, $5 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
|
||||
ginvi 0($4) # CHECK: :[[@LINE]]:10: error: unexpected token in argument list
|
||||
ginvt # CHECK: :[[@LINE]]:3: error: too few operands for instruction
|
||||
ginvt 0 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
|
||||
ginvt $4 # CHECK: :[[@LINE]]:3: error: too few operands for instruction
|
||||
ginvt $4, $5 # CHECK: :[[@LINE]]:13: error: expected 2-bit unsigned immediate
|
||||
ginvt $4, 4 # CHECK: :[[@LINE]]:13: error: expected 2-bit unsigned immediate
|
||||
ginvt $4, -1 # CHECK: :[[@LINE]]:13: error: expected 2-bit unsigned immediate
|
||||
ginvt $4, 0, 1 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
|
||||
ginvt $4, 0($4) # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -mcpu=mips32r6 | \
|
||||
# RUN: FileCheck %s -check-prefix=CHECK-ASM
|
||||
#
|
||||
# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -mcpu=mips32r6 \
|
||||
# RUN: -filetype=obj -o - | \
|
||||
# RUN: llvm-readobj -mips-abi-flags - | \
|
||||
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
|
||||
|
||||
# CHECK-ASM: .module ginv
|
||||
|
||||
# Check if the MIPS.abiflags section was correctly emitted:
|
||||
# CHECK-OBJ: MIPS ABI Flags {
|
||||
# CHECK-OBJ: ASEs [ (0x20000)
|
||||
# CHECK-OBJ: GINV (0x20000)
|
||||
# CHECK-OBJ: }
|
||||
|
||||
.module ginv
|
||||
ginvi $4
|
||||
|
||||
# FIXME: Test should include gnu_attributes directive when implemented.
|
||||
# An explicit .gnu_attribute must be checked against the effective
|
||||
# command line options and any inconsistencies reported via a warning.
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -mattr=+ginv | \
|
||||
# RUN: FileCheck %s -check-prefix=CHECK-ASM
|
||||
#
|
||||
# RUN: llvm-mc %s -arch=mips -mcpu=mips32r6 -filetype=obj -o - -mattr=+ginv | \
|
||||
# RUN: llvm-readobj -mips-abi-flags - | \
|
||||
# RUN: FileCheck %s -check-prefix=CHECK-OBJ
|
||||
|
||||
# CHECK-ASM: .module noginv
|
||||
|
||||
# Check that MIPS.abiflags has no GINV flag.
|
||||
# CHECK-OBJ: MIPS ABI Flags {
|
||||
# CHECK-OBJ: ASEs [ (0x0)
|
||||
# CHECK-OBJ-NOT: ASEs [ (0x20000)
|
||||
# CHECK-OBJ-NOT: GINV (0x20000)
|
||||
# CHECK-OBJ: }
|
||||
|
||||
.module noginv
|
||||
|
||||
# FIXME: Test should include gnu_attributes directive when implemented.
|
||||
# An explicit .gnu_attribute must be checked against the effective
|
||||
# command line options and any inconsistencies reported via a warning.
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
|
||||
# RUN: -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
|
||||
# RUN: llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
|
||||
# RUN: -mcpu=mips64r6 -mattr=+ginv | FileCheck %s
|
||||
|
||||
.set ginv
|
||||
ginvi $4 # CHECK: ginvi $4 # encoding: [0x7c,0x80,0x00,0x3d]
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
# RUN: not llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
|
||||
# RUN: -mcpu=mips32r6 -mattr=+ginv 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
# RUN: not llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
|
||||
# RUN: -mcpu=mips64r6 -mattr=+ginv 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noginv
|
||||
ginvi $4, 2 # CHECK: instruction requires a CPU feature not currently enabled
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
|
||||
# RUN: -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
|
||||
|
||||
ginvi $4 # CHECK: ginvi $4 # encoding: [0x00,0x04,0x61,0x7c]
|
||||
ginvt $4, 2 # CHECK: ginvt $4, 2 # encoding: [0x00,0x04,0x75,0x7c]
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
# RUN: llvm-mc %s -triple=mips-unknown-linux-gnu -show-encoding \
|
||||
# RUN: -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
|
||||
# RUN: llvm-mc %s -triple=mips64-unknown-linux-gnu -show-encoding \
|
||||
# RUN: -mcpu=mips64r6 -mattr=+ginv | FileCheck %s
|
||||
|
||||
ginvi $4 # CHECK: ginvi $4 # encoding: [0x7c,0x80,0x00,0x3d]
|
||||
ginvt $4, 2 # CHECK: ginvt $4, 2 # encoding: [0x7c,0x80,0x02,0xbd]
|
||||
|
|
@ -2233,6 +2233,7 @@ static const EnumEntry<unsigned> ElfMipsASEFlags[] = {
|
|||
{"microMIPS", Mips::AFL_ASE_MICROMIPS},
|
||||
{"XPA", Mips::AFL_ASE_XPA},
|
||||
{"CRC", Mips::AFL_ASE_CRC},
|
||||
{"GINV", Mips::AFL_ASE_GINV},
|
||||
};
|
||||
|
||||
static const EnumEntry<unsigned> ElfMipsFpABIType[] = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue