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[AArch64] CCSIDR2 system register 

Implement the 'Current Cache Size' register that has been introduced
as part of the Armv8.3 architecture. I originally missed this, and
(hopefully) should be the final patch for assembler support.

Differential Revision: https://reviews.llvm.org/D41396

llvm-svn: 321155
This commit is contained in:
Sam Parker 2017-12-20 08:56:41 +00:00
parent 5966d15943
commit daed9de622
4 changed files with 13 additions and 0 deletions
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3
llvm/lib/Target/AArch64/AArch64SystemOperands.td
View File

@ -322,6 +322,9 @@ def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
let Requires = [{ {AArch64::HasV8_3aOps} }];
}
def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;
def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;

3
llvm/test/MC/AArch64/arm64-system-encoding.s
View File

@ -1,4 +1,5 @@
; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
; RUN: not llvm-mc -triple arm64-apple-darwin -mattr=+v8.3a -show-encoding < %s 2> %t | FileCheck %s --check-prefix=CHECK-V83
; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
foo:
@ -233,6 +234,7 @@ foo:
mrs x3, AMAIR_EL3
mrs x3, CCSIDR_EL1
mrs x3, CLIDR_EL1
mrs x3, CCSIDR2_EL1
mrs x3, CNTFRQ_EL0
mrs x3, CNTHCTL_EL2
mrs x3, CNTHP_CTL_EL2
@ -418,6 +420,7 @@ foo:
; CHECK: mrs x3, AMAIR_EL3 ; encoding: [0x03,0xa3,0x3e,0xd5]
; CHECK: mrs x3, CCSIDR_EL1 ; encoding: [0x03,0x00,0x39,0xd5]
; CHECK: mrs x3, CLIDR_EL1 ; encoding: [0x23,0x00,0x39,0xd5]
; CHECK-V83: mrs x3, CCSIDR2_EL1 ; encoding: [0x43,0x00,0x39,0xd5]
; CHECK: mrs x3, CNTFRQ_EL0 ; encoding: [0x03,0xe0,0x3b,0xd5]
; CHECK: mrs x3, CNTHCTL_EL2 ; encoding: [0x03,0xe1,0x3c,0xd5]
; CHECK: mrs x3, CNTHP_CTL_EL2 ; encoding: [0x23,0xe2,0x3c,0xd5]

4
llvm/test/MC/AArch64/basic-a64-diagnostics.s
View File

@ -3504,6 +3504,7 @@
msr MIDR_EL1, x12
msr CCSIDR_EL1, x12
msr CLIDR_EL1, x12
msr CCSIDR2_EL1, x12
msr CTR_EL0, x12
msr MPIDR_EL1, x12
msr REVIDR_EL1, x12
@ -3572,6 +3573,9 @@
// CHECK-ERROR-NEXT: msr CLIDR_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr CCSIDR2_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr CTR_EL0, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate

3
llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt
View File

@ -1,6 +1,7 @@
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
# RUN: llvm-mc -triple=arm64 -mattr=+v8.3a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83
#------------------------------------------------------------------------------
# Add/sub (immediate)
@ -3493,6 +3494,7 @@
# CHECK: mrs x9, {{midr_el1|MIDR_EL1}}
# CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}}
# CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}}
# CHECK-V83: mrs x9, {{ccsidr2_el1|CCSIDR2_EL1}}
# CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}}
# CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}}
# CHECK: mrs x9, {{ctr_el0|CTR_EL0}}
@ -4048,6 +4050,7 @@
0x9 0x0 0x38 0xd5
0x9 0x0 0x39 0xd5
0x9 0x0 0x3a 0xd5
0x49 0x0 0x39 0xd5
0x9 0x0 0x3c 0xd5
0x29 0x0 0x39 0xd5
0x29 0x0 0x3b 0xd5