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When preselecting, favor things that have low depth to select first. This 

is faster and uses less stack space.  This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel

llvm-svn: 23664
This commit is contained in:
Chris Lattner 2005-10-07 22:10:27 +00:00
parent be4bbca0ba
commit dae96f8881
1 changed files with 8 additions and 5 deletions
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11
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -123,6 +123,11 @@ void PPC32DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
SDOperand Node = Worklist.back(); SDOperand Node = Worklist.back();
Worklist.pop_back(); Worklist.pop_back();
// Chose from the least deep of the top two nodes.
if (!Worklist.empty() &&
Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
std::swap(Worklist.back(), Node);
if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END && if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) || Node.Val->getOpcode() < PPCISD::FIRST_NUMBER) ||
CodeGenMap.count(Node)) continue; CodeGenMap.count(Node)) continue;
@ -1026,7 +1031,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops); New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
} }
if (!N->hasOneUse()) CodeGenMap[Op] = New; CodeGenMap[Op] = New;
return New; return New;
} }
case ISD::CopyFromReg: { case ISD::CopyFromReg: {
@ -1042,7 +1047,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
SDOperand Val = Select(N->getOperand(2)); SDOperand Val = Select(N->getOperand(2));
SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other, SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
Chain, Reg, Val); Chain, Reg, Val);
if (!N->hasOneUse()) CodeGenMap[Op] = New; CodeGenMap[Op] = New;
return New; return New;
} }
case ISD::UNDEF: case ISD::UNDEF:
@ -1354,7 +1359,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
Select(N->getOperand(0))); Select(N->getOperand(0)));
return SDOperand(N, 0); return SDOperand(N, 0);
} }
case ISD::LOAD: case ISD::LOAD:
case ISD::EXTLOAD: case ISD::EXTLOAD:
case ISD::ZEXTLOAD: case ISD::ZEXTLOAD:
@ -1402,7 +1406,6 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
return Ext; return Ext;
} }
} }
case ISD::TRUNCSTORE: case ISD::TRUNCSTORE:
case ISD::STORE: { case ISD::STORE: {
SDOperand AddrOp1, AddrOp2; SDOperand AddrOp1, AddrOp2;