forked from OSchip/llvm-project
[ARM] Setting missing isLaneQ attribute on Neon Intrisics definitions
Summary: Some of the `*_laneq` intrinsics defined in arm_neon.td were missing the setting of the `isLaneQ` attribute. This patch sets the attribute on the related definitions, as they will be required to properly perform range checks on their lane arguments. Reviewers: jmolloy, t.p.northover, rsmith, olista01, dnsampaio Reviewed By: dnsampaio Subscribers: dnsampaio, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D74616
This commit is contained in:
Lucas Prates
parent
7bf23563f4
commit
dade859b58
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@ -881,16 +881,22 @@ def COPY_LANE : IOpInst<"vcopy_lane", "..I.I",
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def COPYQ_LANE : IOpInst<"vcopy_lane", "..IqI",
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"QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
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def COPY_LANEQ : IOpInst<"vcopy_laneq", "..IQI",
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"csilPcPsPlUcUsUiUlfd", OP_COPY_LN>;
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"csilPcPsPlUcUsUiUlfd", OP_COPY_LN> {
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let isLaneQ = 1;
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}
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def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "..I.I",
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"QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>;
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"QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN> {
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let isLaneQ = 1;
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}
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////////////////////////////////////////////////////////////////////////////////
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// Set all lanes to same value
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def VDUP_LANE1: WOpInst<"vdup_lane", ".qI", "hdQhQdPlQPl", OP_DUP_LN>;
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def VDUP_LANE2: WOpInst<"vdup_laneq", ".QI",
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"csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl",
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OP_DUP_LN>;
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OP_DUP_LN> {
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let isLaneQ = 1;
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}
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def DUP_N : WOpInst<"vdup_n", ".1", "dQdPlQPl", OP_DUP>;
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def MOV_N : WOpInst<"vmov_n", ".1", "dQdPlQPl", OP_DUP>;
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@ -906,38 +912,60 @@ def CREATE : NoTestOpInst<"vcreate", ".(IU>)", "dPl", OP_CAST> {
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////////////////////////////////////////////////////////////////////////////////
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def VMLA_LANEQ : IOpInst<"vmla_laneq", "...QI",
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"siUsUifQsQiQUsQUiQf", OP_MLA_LN>;
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"siUsUifQsQiQUsQUiQf", OP_MLA_LN> {
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let isLaneQ = 1;
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}
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def VMLS_LANEQ : IOpInst<"vmls_laneq", "...QI",
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"siUsUifQsQiQUsQUiQf", OP_MLS_LN>;
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"siUsUifQsQiQUsQUiQf", OP_MLS_LN> {
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let isLaneQ = 1;
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}
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def VFMA_LANE : IInst<"vfma_lane", "...qI", "fdQfQd">;
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def VFMA_LANEQ : IInst<"vfma_laneq", "...QI", "fdQfQd"> {
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let isLaneQ = 1;
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}
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def VFMS_LANE : IOpInst<"vfms_lane", "...qI", "fdQfQd", OP_FMS_LN>;
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def VFMS_LANEQ : IOpInst<"vfms_laneq", "...QI", "fdQfQd", OP_FMS_LNQ>;
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def VFMS_LANEQ : IOpInst<"vfms_laneq", "...QI", "fdQfQd", OP_FMS_LNQ> {
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let isLaneQ = 1;
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}
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def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLAL_LN>;
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def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLAL_LN> {
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let isLaneQ = 1;
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}
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def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "(>Q)(>Q)Q.I", "siUsUi",
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OP_MLALHi_LN>;
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def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "(>Q)(>Q)QQI", "siUsUi",
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OP_MLALHi_LN>;
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def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLSL_LN>;
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OP_MLALHi_LN> {
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let isLaneQ = 1;
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}
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def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLSL_LN> {
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let isLaneQ = 1;
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}
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def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "(>Q)(>Q)Q.I", "siUsUi",
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OP_MLSLHi_LN>;
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def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "(>Q)(>Q)QQI", "siUsUi",
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OP_MLSLHi_LN>;
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OP_MLSLHi_LN> {
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let isLaneQ = 1;
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}
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def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "(>Q)(>Q).QI", "si", OP_QDMLAL_LN>;
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def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "(>Q)(>Q).QI", "si", OP_QDMLAL_LN> {
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let isLaneQ = 1;
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}
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def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "(>Q)(>Q)Q.I", "si",
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OP_QDMLALHi_LN>;
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def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "(>Q)(>Q)QQI", "si",
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OP_QDMLALHi_LN>;
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def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "(>Q)(>Q).QI", "si", OP_QDMLSL_LN>;
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OP_QDMLALHi_LN> {
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let isLaneQ = 1;
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}
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def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "(>Q)(>Q).QI", "si", OP_QDMLSL_LN> {
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let isLaneQ = 1;
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}
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def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "(>Q)(>Q)Q.I", "si",
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OP_QDMLSLHi_LN>;
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def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "(>Q)(>Q)QQI", "si",
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OP_QDMLSLHi_LN>;
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OP_QDMLSLHi_LN> {
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let isLaneQ = 1;
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}
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// Newly add double parameter for vmul_lane in aarch64
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// Note: d type is handled by SCALAR_VMUL_LANE
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@ -945,32 +973,48 @@ def VMUL_LANE_A64 : IOpInst<"vmul_lane", "..qI", "Qd", OP_MUL_LN>;
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// Note: d type is handled by SCALAR_VMUL_LANEQ
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def VMUL_LANEQ : IOpInst<"vmul_laneq", "..QI",
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"sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN>;
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def VMULL_LANEQ : SOpInst<"vmull_laneq", "(>Q).QI", "siUsUi", OP_MULL_LN>;
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"sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN> {
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let isLaneQ = 1;
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}
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def VMULL_LANEQ : SOpInst<"vmull_laneq", "(>Q).QI", "siUsUi", OP_MULL_LN> {
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let isLaneQ = 1;
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}
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def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "(>Q)Q.I", "siUsUi",
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OP_MULLHi_LN>;
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def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "(>Q)QQI", "siUsUi",
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OP_MULLHi_LN>;
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OP_MULLHi_LN> {
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let isLaneQ = 1;
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}
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def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "(>Q).QI", "si", OP_QDMULL_LN>;
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def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "(>Q).QI", "si", OP_QDMULL_LN> {
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let isLaneQ = 1;
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}
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def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "(>Q)Q.I", "si",
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OP_QDMULLHi_LN>;
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def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "(>Q)QQI", "si",
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OP_QDMULLHi_LN>;
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OP_QDMULLHi_LN> {
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let isLaneQ = 1;
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}
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let isLaneQ = 1 in {
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def VQDMULH_LANEQ : SInst<"vqdmulh_laneq", "..QI", "siQsQi">;
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def VQRDMULH_LANEQ : SInst<"vqrdmulh_laneq", "..QI", "siQsQi">;
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}
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let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in {
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def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "...QI", "siQsQi", OP_QRDMLAH_LN>;
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def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "...QI", "siQsQi", OP_QRDMLSH_LN>;
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def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "...QI", "siQsQi", OP_QRDMLAH_LN> {
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let isLaneQ = 1;
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}
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def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "...QI", "siQsQi", OP_QRDMLSH_LN> {
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let isLaneQ = 1;
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}
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}
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// Note: d type implemented by SCALAR_VMULX_LANE
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def VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "fQfQd", OP_MULX_LN>;
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// Note: d type is implemented by SCALAR_VMULX_LANEQ
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def VMULX_LANEQ : IOpInst<"vmulx_laneq", "..QI", "fQfQd", OP_MULX_LN>;
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def VMULX_LANEQ : IOpInst<"vmulx_laneq", "..QI", "fQfQd", OP_MULX_LN> {
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let isLaneQ = 1;
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}
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////////////////////////////////////////////////////////////////////////////////
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// Across vectors class
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@ -1380,11 +1424,15 @@ def SCALAR_UQXTN : SInst<"vqmovn", "(1<)1", "SUsSUiSUl">;
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// Scalar Floating Point multiply (scalar, by element)
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def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "11.I", "SfSd", OP_SCALAR_MUL_LN>;
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def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "11QI", "SfSd", OP_SCALAR_MUL_LN>;
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def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "11QI", "SfSd", OP_SCALAR_MUL_LN> {
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let isLaneQ = 1;
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}
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// Scalar Floating Point multiply extended (scalar, by element)
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def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "11.I", "SfSd", OP_SCALAR_MULX_LN>;
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def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "11QI", "SfSd", OP_SCALAR_MULX_LN>;
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def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "11QI", "SfSd", OP_SCALAR_MULX_LN> {
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let isLaneQ = 1;
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}
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def SCALAR_VMUL_N : IInst<"vmul_n", "..1", "d">;
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@ -1400,48 +1448,70 @@ def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "..QI", "d"> {
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def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "d", OP_SCALAR_VMULX_LN>;
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// VMULX_LANEQ d type implemented using scalar vmulx_laneq
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def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "..QI", "d", OP_SCALAR_VMULX_LNQ>;
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def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "..QI", "d", OP_SCALAR_VMULX_LNQ> {
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let isLaneQ = 1;
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}
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// Scalar Floating Point fused multiply-add (scalar, by element)
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def SCALAR_FMLA_LANE : IInst<"vfma_lane", "111.I", "SfSd">;
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def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "111QI", "SfSd">;
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def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "111QI", "SfSd"> {
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let isLaneQ = 1;
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}
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// Scalar Floating Point fused multiply-subtract (scalar, by element)
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def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "111.I", "SfSd", OP_FMS_LN>;
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def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "111QI", "SfSd", OP_FMS_LNQ>;
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def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "111QI", "SfSd", OP_FMS_LNQ> {
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let isLaneQ = 1;
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}
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// Signed Saturating Doubling Multiply Long (scalar by element)
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def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "(1>)1.I", "SsSi", OP_SCALAR_QDMULL_LN>;
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def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "(1>)1QI", "SsSi", OP_SCALAR_QDMULL_LN>;
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def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "(1>)1QI", "SsSi", OP_SCALAR_QDMULL_LN> {
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let isLaneQ = 1;
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}
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// Signed Saturating Doubling Multiply-Add Long (scalar by element)
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def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "(1>)(1>)1.I", "SsSi">;
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def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "(1>)(1>)1QI", "SsSi">;
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def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "(1>)(1>)1QI", "SsSi"> {
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let isLaneQ = 1;
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}
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// Signed Saturating Doubling Multiply-Subtract Long (scalar by element)
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def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "(1>)(1>)1.I", "SsSi">;
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def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "(1>)(1>)1QI", "SsSi">;
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def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "(1>)(1>)1QI", "SsSi"> {
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let isLaneQ = 1;
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}
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// Scalar Integer Saturating Doubling Multiply Half High (scalar by element)
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def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "11.I", "SsSi", OP_SCALAR_QDMULH_LN>;
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def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "11QI", "SsSi", OP_SCALAR_QDMULH_LN>;
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def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "11QI", "SsSi", OP_SCALAR_QDMULH_LN> {
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let isLaneQ = 1;
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}
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// Scalar Integer Saturating Rounding Doubling Multiply Half High
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def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "11.I", "SsSi", OP_SCALAR_QRDMULH_LN>;
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def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "11QI", "SsSi", OP_SCALAR_QRDMULH_LN>;
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def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "11QI", "SsSi", OP_SCALAR_QRDMULH_LN> {
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let isLaneQ = 1;
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}
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let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in {
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// Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half
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def SCALAR_SQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "111.I", "SsSi", OP_SCALAR_QRDMLAH_LN>;
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def SCALAR_SQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLAH_LN>;
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def SCALAR_SQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLAH_LN> {
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let isLaneQ = 1;
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}
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// Signed Saturating Rounding Doubling Multiply Subtract Returning High Half
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def SCALAR_SQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "111.I", "SsSi", OP_SCALAR_QRDMLSH_LN>;
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def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLSH_LN>;
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def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLSH_LN> {
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let isLaneQ = 1;
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}
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}
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def SCALAR_VDUP_LANE : IInst<"vdup_lane", "1.I", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
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def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "1QI", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">;
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def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "1QI", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs"> {
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let isLaneQ = 1;
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}
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}
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// ARMv8.2-A FP16 vector intrinsics for A32/A64.
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@ -1605,36 +1675,52 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarc
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// FMA lane
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def VFMA_LANEH : IInst<"vfma_lane", "...qI", "hQh">;
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def VFMA_LANEQH : IInst<"vfma_laneq", "...QI", "hQh">;
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def VFMA_LANEQH : IInst<"vfma_laneq", "...QI", "hQh"> {
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let isLaneQ = 1;
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}
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// FMA lane with scalar argument
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def FMLA_NH : SOpInst<"vfma_n", "...1", "hQh", OP_FMLA_N>;
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// Scalar floating point fused multiply-add (scalar, by element)
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def SCALAR_FMLA_LANEH : IInst<"vfma_lane", "111.I", "Sh">;
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def SCALAR_FMLA_LANEQH : IInst<"vfma_laneq", "111QI", "Sh">;
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def SCALAR_FMLA_LANEQH : IInst<"vfma_laneq", "111QI", "Sh"> {
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let isLaneQ = 1;
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}
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// FMS lane
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def VFMS_LANEH : IOpInst<"vfms_lane", "...qI", "hQh", OP_FMS_LN>;
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def VFMS_LANEQH : IOpInst<"vfms_laneq", "...QI", "hQh", OP_FMS_LNQ>;
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def VFMS_LANEQH : IOpInst<"vfms_laneq", "...QI", "hQh", OP_FMS_LNQ> {
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let isLaneQ = 1;
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}
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// FMS lane with scalar argument
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def FMLS_NH : SOpInst<"vfms_n", "...1", "hQh", OP_FMLS_N>;
|
||||
// Scalar floating foint fused multiply-subtract (scalar, by element)
|
||||
def SCALAR_FMLS_LANEH : IOpInst<"vfms_lane", "111.I", "Sh", OP_FMS_LN>;
|
||||
def SCALAR_FMLS_LANEQH : IOpInst<"vfms_laneq", "111QI", "Sh", OP_FMS_LNQ>;
|
||||
def SCALAR_FMLS_LANEQH : IOpInst<"vfms_laneq", "111QI", "Sh", OP_FMS_LNQ> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
|
||||
// Mul lane
|
||||
def VMUL_LANEQH : IOpInst<"vmul_laneq", "..QI", "hQh", OP_MUL_LN>;
|
||||
def VMUL_LANEQH : IOpInst<"vmul_laneq", "..QI", "hQh", OP_MUL_LN> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
// Scalar floating point multiply (scalar, by element)
|
||||
def SCALAR_FMUL_LANEH : IOpInst<"vmul_lane", "11.I", "Sh", OP_SCALAR_MUL_LN>;
|
||||
def SCALAR_FMUL_LANEQH : IOpInst<"vmul_laneq", "11QI", "Sh", OP_SCALAR_MUL_LN>;
|
||||
def SCALAR_FMUL_LANEQH : IOpInst<"vmul_laneq", "11QI", "Sh", OP_SCALAR_MUL_LN> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
|
||||
// Mulx lane
|
||||
def VMULX_LANEH : IOpInst<"vmulx_lane", "..qI", "hQh", OP_MULX_LN>;
|
||||
def VMULX_LANEQH : IOpInst<"vmulx_laneq", "..QI", "hQh", OP_MULX_LN>;
|
||||
def VMULX_LANEQH : IOpInst<"vmulx_laneq", "..QI", "hQh", OP_MULX_LN> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
def VMULX_NH : IOpInst<"vmulx_n", "..1", "hQh", OP_MULX_N>;
|
||||
// Scalar floating point mulx (scalar, by element)
|
||||
def SCALAR_FMULX_LANEH : IInst<"vmulx_lane", "11.I", "Sh">;
|
||||
def SCALAR_FMULX_LANEQH : IInst<"vmulx_laneq", "11QI", "Sh">;
|
||||
def SCALAR_FMULX_LANEQH : IInst<"vmulx_laneq", "11QI", "Sh"> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
|
||||
// ARMv8.2-A FP16 reduction vector intrinsics.
|
||||
def VMAXVH : SInst<"vmaxv", "1.", "hQh">;
|
||||
|
|
@ -1651,7 +1737,9 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarc
|
|||
def VUZP2H : SOpInst<"vuzp2", "...", "hQh", OP_UZP2>;
|
||||
|
||||
def SCALAR_VDUP_LANEH : IInst<"vdup_lane", "1.I", "Sh">;
|
||||
def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "1QI", "Sh">;
|
||||
def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "1QI", "Sh"> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
}
|
||||
|
||||
// v8.2-A dot product instructions.
|
||||
|
|
@ -1661,7 +1749,9 @@ let ArchGuard = "defined(__ARM_FEATURE_DOTPROD)" in {
|
|||
}
|
||||
let ArchGuard = "defined(__ARM_FEATURE_DOTPROD) && defined(__aarch64__)" in {
|
||||
// Variants indexing into a 128-bit vector are A64 only.
|
||||
def UDOT_LANEQ : SOpInst<"vdot_laneq", "..(<<)(<<Q)I", "iUiQiQUi", OP_DOT_LNQ>;
|
||||
def UDOT_LANEQ : SOpInst<"vdot_laneq", "..(<<)(<<Q)I", "iUiQiQUi", OP_DOT_LNQ> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
}
|
||||
|
||||
// v8.2-A FP16 fused multiply-add long instructions.
|
||||
|
|
@ -1676,10 +1766,18 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16FML) && defined(__aarch64__)" in {
|
|||
def VFMLAL_LANE_HIGH : SOpInst<"vfmlal_lane_high", "(F>)(F>)F(Fq)I", "hQh", OP_FMLAL_LN_Hi>;
|
||||
def VFMLSL_LANE_HIGH : SOpInst<"vfmlsl_lane_high", "(F>)(F>)F(Fq)I", "hQh", OP_FMLSL_LN_Hi>;
|
||||
|
||||
def VFMLAL_LANEQ_LOW : SOpInst<"vfmlal_laneq_low", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN>;
|
||||
def VFMLSL_LANEQ_LOW : SOpInst<"vfmlsl_laneq_low", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN>;
|
||||
def VFMLAL_LANEQ_HIGH : SOpInst<"vfmlal_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN_Hi>;
|
||||
def VFMLSL_LANEQ_HIGH : SOpInst<"vfmlsl_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN_Hi>;
|
||||
def VFMLAL_LANEQ_LOW : SOpInst<"vfmlal_laneq_low", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
def VFMLSL_LANEQ_LOW : SOpInst<"vfmlsl_laneq_low", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
def VFMLAL_LANEQ_HIGH : SOpInst<"vfmlal_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN_Hi> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
def VFMLSL_LANEQ_HIGH : SOpInst<"vfmlsl_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN_Hi> {
|
||||
let isLaneQ = 1;
|
||||
}
|
||||
}
|
||||
|
||||
// v8.3-A Vector complex addition intrinsics
|
||||
|
|
|
|||
Loading…
Reference in New Issue