From dacf057bdc8eb1c16ff99106c667e063c73bf82a Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Mon, 5 Jan 2015 21:36:38 +0000 Subject: [PATCH] [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references. llvm-svn: 225210 --- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 86 +++--- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 268 ++++++------------ llvm/test/MC/Disassembler/Hexagon/memop.txt | 50 ++++ .../MC/Disassembler/Hexagon/xtype_alu.txt | 4 + .../MC/Disassembler/Hexagon/xtype_shift.txt | 2 + 5 files changed, 182 insertions(+), 228 deletions(-) create mode 100644 llvm/test/MC/Disassembler/Hexagon/memop.txt diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 1e2167f16f32..7959b7074149 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1128,28 +1128,28 @@ isValidOffset(const int Opcode, const int Offset) const { return (Offset >= Hexagon_ADDI_OFFSET_MIN) && (Offset <= Hexagon_ADDI_OFFSET_MAX); - case Hexagon::MemOPw_ADDi_V4 : - case Hexagon::MemOPw_SUBi_V4 : - case Hexagon::MemOPw_ADDr_V4 : - case Hexagon::MemOPw_SUBr_V4 : - case Hexagon::MemOPw_ANDr_V4 : - case Hexagon::MemOPw_ORr_V4 : + case Hexagon::L4_iadd_memopw_io: + case Hexagon::L4_isub_memopw_io: + case Hexagon::L4_add_memopw_io: + case Hexagon::L4_sub_memopw_io: + case Hexagon::L4_and_memopw_io: + case Hexagon::L4_or_memopw_io: return (0 <= Offset && Offset <= 255); - case Hexagon::MemOPh_ADDi_V4 : - case Hexagon::MemOPh_SUBi_V4 : - case Hexagon::MemOPh_ADDr_V4 : - case Hexagon::MemOPh_SUBr_V4 : - case Hexagon::MemOPh_ANDr_V4 : - case Hexagon::MemOPh_ORr_V4 : + case Hexagon::L4_iadd_memoph_io: + case Hexagon::L4_isub_memoph_io: + case Hexagon::L4_add_memoph_io: + case Hexagon::L4_sub_memoph_io: + case Hexagon::L4_and_memoph_io: + case Hexagon::L4_or_memoph_io: return (0 <= Offset && Offset <= 127); - case Hexagon::MemOPb_ADDi_V4 : - case Hexagon::MemOPb_SUBi_V4 : - case Hexagon::MemOPb_ADDr_V4 : - case Hexagon::MemOPb_SUBr_V4 : - case Hexagon::MemOPb_ANDr_V4 : - case Hexagon::MemOPb_ORr_V4 : + case Hexagon::L4_iadd_memopb_io: + case Hexagon::L4_isub_memopb_io: + case Hexagon::L4_add_memopb_io: + case Hexagon::L4_sub_memopb_io: + case Hexagon::L4_and_memopb_io: + case Hexagon::L4_or_memopb_io: return (0 <= Offset && Offset <= 63); // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of @@ -1206,31 +1206,31 @@ isMemOp(const MachineInstr *MI) const { switch (MI->getOpcode()) { - default: return false; - case Hexagon::MemOPw_ADDi_V4 : - case Hexagon::MemOPw_SUBi_V4 : - case Hexagon::MemOPw_ADDr_V4 : - case Hexagon::MemOPw_SUBr_V4 : - case Hexagon::MemOPw_ANDr_V4 : - case Hexagon::MemOPw_ORr_V4 : - case Hexagon::MemOPh_ADDi_V4 : - case Hexagon::MemOPh_SUBi_V4 : - case Hexagon::MemOPh_ADDr_V4 : - case Hexagon::MemOPh_SUBr_V4 : - case Hexagon::MemOPh_ANDr_V4 : - case Hexagon::MemOPh_ORr_V4 : - case Hexagon::MemOPb_ADDi_V4 : - case Hexagon::MemOPb_SUBi_V4 : - case Hexagon::MemOPb_ADDr_V4 : - case Hexagon::MemOPb_SUBr_V4 : - case Hexagon::MemOPb_ANDr_V4 : - case Hexagon::MemOPb_ORr_V4 : - case Hexagon::MemOPb_SETBITi_V4: - case Hexagon::MemOPh_SETBITi_V4: - case Hexagon::MemOPw_SETBITi_V4: - case Hexagon::MemOPb_CLRBITi_V4: - case Hexagon::MemOPh_CLRBITi_V4: - case Hexagon::MemOPw_CLRBITi_V4: + default: return false; + case Hexagon::L4_iadd_memopw_io: + case Hexagon::L4_isub_memopw_io: + case Hexagon::L4_add_memopw_io: + case Hexagon::L4_sub_memopw_io: + case Hexagon::L4_and_memopw_io: + case Hexagon::L4_or_memopw_io: + case Hexagon::L4_iadd_memoph_io: + case Hexagon::L4_isub_memoph_io: + case Hexagon::L4_add_memoph_io: + case Hexagon::L4_sub_memoph_io: + case Hexagon::L4_and_memoph_io: + case Hexagon::L4_or_memoph_io: + case Hexagon::L4_iadd_memopb_io: + case Hexagon::L4_isub_memopb_io: + case Hexagon::L4_add_memopb_io: + case Hexagon::L4_sub_memopb_io: + case Hexagon::L4_and_memopb_io: + case Hexagon::L4_or_memopb_io: + case Hexagon::L4_ior_memopb_io: + case Hexagon::L4_ior_memoph_io: + case Hexagon::L4_ior_memopw_io: + case Hexagon::L4_iand_memopb_io: + case Hexagon::L4_iand_memoph_io: + case Hexagon::L4_iand_memopw_io: return true; } return false; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index ae7b7d497e16..159700b9a1cd 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -2239,158 +2239,54 @@ let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>; -// Shift by immediate and accumulate. -// Rx=add(#u8,asl(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, -validSubTargets = HasV4SubT in -def ADDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst), - (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3), - "$dst = add(#$src1, asl($src2, #$src3))", - [(set (i32 IntRegs:$dst), - (add (shl (i32 IntRegs:$src2), u5ImmPred:$src3), - u8ExtPred:$src1))], - "$src2 = $dst">, - Requires<[HasV4T]>; +// Rdd=[add|sub](Rss,Rtt,Px):carry +let isPredicateLate = 1, hasSideEffects = 0 in +class T_S3op_carry MajOp> + : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px), + (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu), + "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry", + [], "$Px = $Pu", S_3op_tc_1_SLOT23 > { + bits<5> Rdd; + bits<5> Rss; + bits<5> Rtt; + bits<2> Pu; -// Rx=add(#u8,lsr(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, -validSubTargets = HasV4SubT in -def ADDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst), - (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3), - "$dst = add(#$src1, lsr($src2, #$src3))", - [(set (i32 IntRegs:$dst), - (add (srl (i32 IntRegs:$src2), u5ImmPred:$src3), - u8ExtPred:$src1))], - "$src2 = $dst">, - Requires<[HasV4T]>; + let IClass = 0b1100; -// Rx=sub(#u8,asl(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, -validSubTargets = HasV4SubT in -def SUBi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst), - (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3), - "$dst = sub(#$src1, asl($src2, #$src3))", - [(set (i32 IntRegs:$dst), - (sub (shl (i32 IntRegs:$src2), u5ImmPred:$src3), - u8ExtPred:$src1))], - "$src2 = $dst">, - Requires<[HasV4T]>; + let Inst{27-24} = 0b0010; + let Inst{23-21} = MajOp; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + let Inst{6-5} = Pu; + let Inst{4-0} = Rdd; + } -// Rx=sub(#u8,lsr(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, -validSubTargets = HasV4SubT in -def SUBi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst), - (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3), - "$dst = sub(#$src1, lsr($src2, #$src3))", - [(set (i32 IntRegs:$dst), - (sub (srl (i32 IntRegs:$src2), u5ImmPred:$src3), - u8ExtPred:$src1))], - "$src2 = $dst">, - Requires<[HasV4T]>; - - -//Shift by immediate and logical. -//Rx=and(#u8,asl(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, -validSubTargets = HasV4SubT in -def ANDi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst), - (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3), - "$dst = and(#$src1, asl($src2, #$src3))", - [(set (i32 IntRegs:$dst), - (and (shl (i32 IntRegs:$src2), u5ImmPred:$src3), - u8ExtPred:$src1))], - "$src2 = $dst">, - Requires<[HasV4T]>; - -//Rx=and(#u8,lsr(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, -validSubTargets = HasV4SubT in -def ANDi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst), - (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3), - "$dst = and(#$src1, lsr($src2, #$src3))", - [(set (i32 IntRegs:$dst), - (and (srl (i32 IntRegs:$src2), u5ImmPred:$src3), - u8ExtPred:$src1))], - "$src2 = $dst">, - Requires<[HasV4T]>; - -//Rx=or(#u8,asl(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, -AddedComplexity = 30, validSubTargets = HasV4SubT in -def ORi_ASLri_V4 : MInst_acc<(outs IntRegs:$dst), - (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3), - "$dst = or(#$src1, asl($src2, #$src3))", - [(set (i32 IntRegs:$dst), - (or (shl (i32 IntRegs:$src2), u5ImmPred:$src3), - u8ExtPred:$src1))], - "$src2 = $dst">, - Requires<[HasV4T]>; - -//Rx=or(#u8,lsr(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, -AddedComplexity = 30, validSubTargets = HasV4SubT in -def ORi_LSRri_V4 : MInst_acc<(outs IntRegs:$dst), - (ins u8Ext:$src1, IntRegs:$src2, u5Imm:$src3), - "$dst = or(#$src1, lsr($src2, #$src3))", - [(set (i32 IntRegs:$dst), - (or (srl (i32 IntRegs:$src2), u5ImmPred:$src3), - u8ExtPred:$src1))], - "$src2 = $dst">, - Requires<[HasV4T]>; - - -//Shift by register. -//Rd=lsl(#s6,Rt) -let validSubTargets = HasV4SubT in { -def LSLi_V4 : MInst<(outs IntRegs:$dst), (ins s6Imm:$src1, IntRegs:$src2), - "$dst = lsl(#$src1, $src2)", - [(set (i32 IntRegs:$dst), (shl s6ImmPred:$src1, - (i32 IntRegs:$src2)))]>, - Requires<[HasV4T]>; - - -//Shift by register and logical. -//Rxx^=asl(Rss,Rt) -def ASLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst), - (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - "$dst ^= asl($src2, $src3)", - [(set (i64 DoubleRegs:$dst), - (xor (i64 DoubleRegs:$src1), (shl (i64 DoubleRegs:$src2), - (i32 IntRegs:$src3))))], - "$src1 = $dst">, - Requires<[HasV4T]>; - -//Rxx^=asr(Rss,Rt) -def ASRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst), - (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - "$dst ^= asr($src2, $src3)", - [(set (i64 DoubleRegs:$dst), - (xor (i64 DoubleRegs:$src1), (sra (i64 DoubleRegs:$src2), - (i32 IntRegs:$src3))))], - "$src1 = $dst">, - Requires<[HasV4T]>; - -//Rxx^=lsl(Rss,Rt) -def LSLd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst), - (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - "$dst ^= lsl($src2, $src3)", - [(set (i64 DoubleRegs:$dst), (xor (i64 DoubleRegs:$src1), - (shl (i64 DoubleRegs:$src2), - (i32 IntRegs:$src3))))], - "$src1 = $dst">, - Requires<[HasV4T]>; - -//Rxx^=lsr(Rss,Rt) -def LSRd_rr_xor_V4 : MInst_acc<(outs DoubleRegs:$dst), - (ins DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3), - "$dst ^= lsr($src2, $src3)", - [(set (i64 DoubleRegs:$dst), - (xor (i64 DoubleRegs:$src1), (srl (i64 DoubleRegs:$src2), - (i32 IntRegs:$src3))))], - "$src1 = $dst">, - Requires<[HasV4T]>; +let isCodeGenOnly = 0 in { +def A4_addp_c : T_S3op_carry < "add", 0b110 >; +def A4_subp_c : T_S3op_carry < "sub", 0b111 >; } +// Shift an immediate left by register amount. +let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in +def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt), + "$Rd = lsl(#$s6, $Rt)" , + [(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6, + (i32 IntRegs:$Rt)))], + "", S_3op_tc_1_SLOT23> { + bits<5> Rd; + bits<6> s6; + bits<5> Rt; + + let IClass = 0b1100; + + let Inst{27-22} = 0b011010; + let Inst{20-16} = s6{5-1}; + let Inst{12-8} = Rt; + let Inst{7-6} = 0b11; + let Inst{4-0} = Rd; + let Inst{5} = s6{0}; + } + //===----------------------------------------------------------------------===// // XTYPE/SHIFT - //===----------------------------------------------------------------------===// @@ -2478,7 +2374,7 @@ class MemOp_rr_base opcBits, Operand ImmOp, (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta), opc#"($base+#$offset)"#memOp#"$delta", []>, - Requires<[HasV4T, UseMEMOP]> { + Requires<[UseMEMOP]> { bits<5> base; bits<5> delta; @@ -2489,6 +2385,7 @@ class MemOp_rr_base opcBits, Operand ImmOp, !if (!eq(opcBits, 0b01), offset{6-1}, !if (!eq(opcBits, 0b10), offset{7-2},0))); + let opExtentAlign = opcBits; let IClass = 0b0011; let Inst{27-24} = 0b1110; let Inst{22-21} = opcBits; @@ -2509,7 +2406,7 @@ class MemOp_ri_base opcBits, Operand ImmOp, opc#"($base+#$offset)"#memOp#"#$delta" #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')' []>, - Requires<[HasV4T, UseMEMOP]> { + Requires<[UseMEMOP]> { bits<5> base; bits<5> delta; @@ -2520,6 +2417,7 @@ class MemOp_ri_base opcBits, Operand ImmOp, !if (!eq(opcBits, 0b01), offset{6-1}, !if (!eq(opcBits, 0b10), offset{7-2},0))); + let opExtentAlign = opcBits; let IClass = 0b0011; let Inst{27-24} = 0b1111; let Inst{22-21} = opcBits; @@ -2532,36 +2430,36 @@ class MemOp_ri_base opcBits, Operand ImmOp, // multiclass to define MemOp instructions with register operand. multiclass MemOp_rr opcBits, Operand ImmOp> { - def _ADD#NAME#_V4 : MemOp_rr_base ; - def _SETBIT#NAME#_V4 : MemOp_ri_base; + def L4_iadd#NAME : MemOp_ri_base ; + def L4_ior#NAME : MemOp_ri_base; } multiclass MemOp_base opcBits, Operand ImmOp> { - defm r : MemOp_rr ; - defm i : MemOp_ri ; + defm _#NAME : MemOp_rr ; + defm _#NAME : MemOp_ri ; } // Define MemOp instructions. let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, -validSubTargets =HasV4SubT in { - let opExtentBits = 6, accessSize = ByteAccess in - defm MemOPb : MemOp_base <"memb", 0b00, u6_0Ext>; + validSubTargets =HasV4SubT in { + let opExtentBits = 6, accessSize = ByteAccess, isCodeGenOnly = 0 in + defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>; - let opExtentBits = 7, accessSize = HalfWordAccess in - defm MemOPh : MemOp_base <"memh", 0b01, u6_1Ext>; + let opExtentBits = 7, accessSize = HalfWordAccess, isCodeGenOnly = 0 in + defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>; - let opExtentBits = 8, accessSize = WordAccess in - defm MemOPw : MemOp_base <"memw", 0b10, u6_2Ext>; + let opExtentBits = 8, accessSize = WordAccess, isCodeGenOnly = 0 in + defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>; } //===----------------------------------------------------------------------===// @@ -2594,10 +2492,10 @@ multiclass MemOpi_u5ALUOp { // Half Word defm : MemOpi_u5ALUOp ; + L4_iadd_memoph_io, L4_isub_memoph_io>; // Byte defm : MemOpi_u5ALUOp ; + L4_iadd_memopb_io, L4_isub_memopb_io>; } let Predicates = [HasV4T, UseMEMOP] in { @@ -2606,8 +2504,8 @@ let Predicates = [HasV4T, UseMEMOP] in { defm : MemOpi_u5ExtType; // any extend // Word - defm : MemOpi_u5ALUOp ; + defm : MemOpi_u5ALUOp ; } //===----------------------------------------------------------------------===// @@ -2635,10 +2533,10 @@ multiclass MemOpi_m5Pats { // Half Word defm : MemOpi_m5Pats ; + ADDRriU6_1, MEMOPIMM_HALF, L4_isub_memoph_io>; // Byte defm : MemOpi_m5Pats ; + ADDRriU6_0, MEMOPIMM_BYTE, L4_isub_memopb_io>; } let Predicates = [HasV4T, UseMEMOP] in { @@ -2648,7 +2546,7 @@ let Predicates = [HasV4T, UseMEMOP] in { // Word defm : MemOpi_m5Pats ; + ADDRriU6_2, MEMOPIMM, L4_isub_memopw_io>; } //===----------------------------------------------------------------------===// @@ -2679,16 +2577,16 @@ multiclass MemOpi_bitPats { // Byte - clrbit defm : MemOpi_bitPats; + ADDRriU6_0, CLRMEMIMM_BYTE, L4_iand_memopb_io, and>; // Byte - setbit defm : MemOpi_bitPats; + ADDRriU6_0, SETMEMIMM_BYTE, L4_ior_memopb_io, or>; // Half Word - clrbit defm : MemOpi_bitPats; + ADDRriU6_1, CLRMEMIMM_SHORT, L4_iand_memoph_io, and>; // Half Word - setbit defm : MemOpi_bitPats; + ADDRriU6_1, SETMEMIMM_SHORT, L4_ior_memoph_io, or>; } let Predicates = [HasV4T, UseMEMOP] in { @@ -2701,9 +2599,9 @@ let Predicates = [HasV4T, UseMEMOP] in { // memw(Rs+#0) = [clrbit|setbit](#U5) // memw(Rs+#u6:2) = [clrbit|setbit](#U5) defm : MemOpi_bitPats; + CLRMEMIMM, L4_iand_memopw_io, and>; defm : MemOpi_bitPats; + SETMEMIMM, L4_ior_memopw_io, or>; } //===----------------------------------------------------------------------===// @@ -2744,12 +2642,12 @@ multiclass MemOPr_ALUOp { // Half Word defm : MemOPr_ALUOp ; + L4_add_memoph_io, L4_sub_memoph_io, + L4_and_memoph_io, L4_or_memoph_io>; // Byte defm : MemOPr_ALUOp ; + L4_add_memopb_io, L4_sub_memopb_io, + L4_and_memopb_io, L4_or_memopb_io>; } // Define 'def Pats' for MemOps with register addend. @@ -2759,8 +2657,8 @@ let Predicates = [HasV4T, UseMEMOP] in { defm : MemOPr_ExtType; // sign extend defm : MemOPr_ExtType; // any extend // Word - defm : MemOPr_ALUOp ; + defm : MemOPr_ALUOp ; } //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/Disassembler/Hexagon/memop.txt b/llvm/test/MC/Disassembler/Hexagon/memop.txt new file mode 100644 index 000000000000..7c944121ddcc --- /dev/null +++ b/llvm/test/MC/Disassembler/Hexagon/memop.txt @@ -0,0 +1,50 @@ +# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s + +0x95 0xd9 0x11 0x3e +# CHECK: memb(r17+#51) += r21 +0xb5 0xd9 0x11 0x3e +# CHECK: memb(r17+#51) -= r21 +0xd5 0xd9 0x11 0x3e +# CHECK: memb(r17+#51) &= r21 +0xf5 0xd9 0x11 0x3e +# CHECK: memb(r17+#51) |= r21 +0x95 0xd9 0x11 0x3f +# CHECK: memb(r17+#51) += #21 +0xb5 0xd9 0x11 0x3f +# CHECK: memb(r17+#51) -= #21 +0xd5 0xd9 0x11 0x3f +# CHECK: memb(r17+#51) = clrbit(#21) +0xf5 0xd9 0x11 0x3f +# CHECK: memb(r17+#51) = setbit(#21) +0x95 0xd9 0x31 0x3e +# CHECK: memh(r17+#102) += r21 +0xb5 0xd9 0x31 0x3e +# CHECK: memh(r17+#102) -= r21 +0xd5 0xd9 0x31 0x3e +# CHECK: memh(r17+#102) &= r21 +0xf5 0xd9 0x31 0x3e +# CHECK: memh(r17+#102) |= r21 +0x95 0xd9 0x31 0x3f +# CHECK: memh(r17+#102) += #21 +0xb5 0xd9 0x31 0x3f +# CHECK: memh(r17+#102) -= #21 +0xd5 0xd9 0x31 0x3f +# CHECK: memh(r17+#102) = clrbit(#21) +0xf5 0xd9 0x31 0x3f +# CHECK: memh(r17+#102) = setbit(#21) +0x95 0xd9 0x51 0x3e +# CHECK: memw(r17+#204) += r21 +0xb5 0xd9 0x51 0x3e +# CHECK: memw(r17+#204) -= r21 +0xd5 0xd9 0x51 0x3e +# CHECK: memw(r17+#204) &= r21 +0xf5 0xd9 0x51 0x3e +# CHECK: memw(r17+#204) |= r21 +0x95 0xd9 0x51 0x3f +# CHECK: memw(r17+#204) += #21 +0xb5 0xd9 0x51 0x3f +# CHECK: memw(r17+#204) -= #21 +0xd5 0xd9 0x51 0x3f +# CHECK: memw(r17+#204) = clrbit(#21) +0xf5 0xd9 0x51 0x3f +# CHECK: memw(r17+#204) = setbit(#21) diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt index b86165e496e3..d39260c63228 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_alu.txt @@ -44,6 +44,10 @@ # CHECK: r17 = add(r21.h, r31.l):sat:<<16 0xf1 0xd5 0x5f 0xd5 # CHECK: r17 = add(r21.h, r31.h):sat:<<16 +0x70 0xde 0xd4 0xc2 +# CHECK: r17:16 = add(r21:20, r31:30, p3):carry +0x70 0xde 0xf4 0xc2 +# CHECK: r17:16 = sub(r21:20, r31:30, p3):carry 0x90 0xc0 0x94 0x80 # CHECK: r17:16 = not(r21:20) 0xf0 0xde 0x14 0xd3 diff --git a/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt b/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt index 5e26c1b669bf..1a0fbe418527 100644 --- a/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt +++ b/llvm/test/MC/Disassembler/Hexagon/xtype_shift.txt @@ -106,6 +106,8 @@ # CHECK: r17 = asl(r21, r31) 0xd1 0xdf 0x55 0xc6 # CHECK: r17 = lsl(r21, r31) +0xf1 0xdf 0x8a 0xc6 +# CHECK: r17 = lsl(#21, r31) 0x10 0xdf 0x94 0xcb # CHECK: r17:16 -= asr(r21:20, r31) 0x50 0xdf 0x94 0xcb