forked from OSchip/llvm-project
[AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsic
This intrinsic selects v_mad_f32 regardless of fp32 denorm support. Differential Revision: https://reviews.llvm.org/D48573 llvm-svn: 335654
This commit is contained in:
Stanislav Mekhanoshin
parent
2a2945a3c5
commit
dacda79ee6
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@ -360,6 +360,12 @@ def int_amdgcn_sffbh :
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[IntrNoMem, IntrSpeculatable]
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>;
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// v_mad_f32/v_mac_f32, selected regardless of denorm support.
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def int_amdgcn_fmad_ftz :
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty],
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[IntrNoMem, IntrSpeculatable]
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>;
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// Fields should mirror atomicrmw
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class AMDGPUAtomicIncIntrin : Intrinsic<[llvm_anyint_ty],
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@ -4922,6 +4922,9 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return SDValue(DAG.getMachineNode(AMDGPU::WWM, DL, Src.getValueType(), Src),
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0);
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}
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case Intrinsic::amdgcn_fmad_ftz:
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return DAG.getNode(AMDGPUISD::FMAD_FTZ, DL, VT, Op.getOperand(1),
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Op.getOperand(2), Op.getOperand(3));
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default:
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if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
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AMDGPU::getImageDimIntrinsicInfo(IntrinsicID))
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@ -0,0 +1,114 @@
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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declare float @llvm.amdgcn.fmad.ftz(float %a, float %b, float %c)
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; GCN-LABEL: {{^}}mad_f32:
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; GCN: v_ma{{[dc]}}_f32
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define amdgpu_kernel void @mad_f32(
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %b,
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float addrspace(1)* %c) {
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%a.val = load float, float addrspace(1)* %a
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%b.val = load float, float addrspace(1)* %b
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%c.val = load float, float addrspace(1)* %c
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%r.val = call float @llvm.amdgcn.fmad.ftz(float %a.val, float %b.val, float %c.val)
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}mad_f32_imm_a:
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; GCN: v_mov_b32_e32 [[KA:v[0-9]+]], 0x41000000
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; GCN: v_ma{{[dc]}}_f32 {{v[0-9]+}}, [[KA]],
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define amdgpu_kernel void @mad_f32_imm_a(
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float addrspace(1)* %r,
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float addrspace(1)* %b,
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float addrspace(1)* %c) {
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%b.val = load float, float addrspace(1)* %b
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%c.val = load float, float addrspace(1)* %c
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%r.val = call float @llvm.amdgcn.fmad.ftz(float 8.0, float %b.val, float %c.val)
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}mad_f32_imm_b:
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; GCN: v_mov_b32_e32 [[KB:v[0-9]+]], 0x41000000
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; GCN: v_ma{{[dc]}}_f32 {{v[0-9]+}}, {{[vs][0-9]+}}, [[KB]],
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define amdgpu_kernel void @mad_f32_imm_b(
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %c) {
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%a.val = load float, float addrspace(1)* %a
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%c.val = load float, float addrspace(1)* %c
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%r.val = call float @llvm.amdgcn.fmad.ftz(float %a.val, float 8.0, float %c.val)
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}mad_f32_imm_c:
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; GCN: v_mov_b32_e32 [[KC:v[0-9]+]], 0x41000000
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; GCN: v_ma{{[dc]}}_f32 {{v[0-9]+}}, {{[vs][0-9]+}}, {{v[0-9]+}}, [[KC]]{{$}}
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define amdgpu_kernel void @mad_f32_imm_c(
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %b) {
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%a.val = load float, float addrspace(1)* %a
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%b.val = load float, float addrspace(1)* %b
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%r.val = call float @llvm.amdgcn.fmad.ftz(float %a.val, float %b.val, float 8.0)
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}mad_f32_neg_b:
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; GCN: v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @mad_f32_neg_b(
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %b,
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float addrspace(1)* %c) {
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%a.val = load float, float addrspace(1)* %a
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%b.val = load float, float addrspace(1)* %b
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%c.val = load float, float addrspace(1)* %c
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%neg.b = fsub float -0.0, %b.val
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%r.val = call float @llvm.amdgcn.fmad.ftz(float %a.val, float %neg.b, float %c.val)
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}mad_f32_abs_b:
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; GCN: v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, |v{{[0-9]+}}|, v{{[0-9]+}}
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define amdgpu_kernel void @mad_f32_abs_b(
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %b,
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float addrspace(1)* %c) {
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%a.val = load float, float addrspace(1)* %a
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%b.val = load float, float addrspace(1)* %b
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%c.val = load float, float addrspace(1)* %c
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%abs.b = call float @llvm.fabs.f32(float %b.val)
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%r.val = call float @llvm.amdgcn.fmad.ftz(float %a.val, float %abs.b, float %c.val)
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}mad_f32_neg_abs_b:
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; GCN: v_mad_f32 v{{[0-9]+}}, s{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}}
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define amdgpu_kernel void @mad_f32_neg_abs_b(
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float addrspace(1)* %r,
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float addrspace(1)* %a,
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float addrspace(1)* %b,
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float addrspace(1)* %c) {
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%a.val = load float, float addrspace(1)* %a
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%b.val = load float, float addrspace(1)* %b
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%c.val = load float, float addrspace(1)* %c
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%abs.b = call float @llvm.fabs.f32(float %b.val)
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%neg.abs.b = fsub float -0.0, %abs.b
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%r.val = call float @llvm.amdgcn.fmad.ftz(float %a.val, float %neg.abs.b, float %c.val)
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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declare float @llvm.fabs.f32(float)
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