forked from OSchip/llvm-project
[RISCV] Move isValidCPUName to RISCVTargetInfo. NFC
Instead of having separate implementations for RV32 and RV64, use the triple to control the Is64Bit parameter. Do the same for isValidTuneCPUName, fillValidCPUList, and fillValidTuneCPUList.
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@ -285,44 +285,25 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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return true;
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}
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bool RISCV32TargetInfo::isValidCPUName(StringRef Name) const {
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return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name),
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/*Is64Bit=*/false);
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bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
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bool Is64Bit = getTriple().isArch64Bit();
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return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name), Is64Bit);
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}
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void RISCV32TargetInfo::fillValidCPUList(
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void RISCVTargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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llvm::RISCV::fillValidCPUArchList(Values, false);
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bool Is64Bit = getTriple().isArch64Bit();
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llvm::RISCV::fillValidCPUArchList(Values, Is64Bit);
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}
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bool RISCV32TargetInfo::isValidTuneCPUName(StringRef Name) const {
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bool RISCVTargetInfo::isValidTuneCPUName(StringRef Name) const {
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bool Is64Bit = getTriple().isArch64Bit();
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return llvm::RISCV::checkTuneCPUKind(
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llvm::RISCV::parseTuneCPUKind(Name, false),
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/*Is64Bit=*/false);
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llvm::RISCV::parseTuneCPUKind(Name, Is64Bit), Is64Bit);
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}
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void RISCV32TargetInfo::fillValidTuneCPUList(
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void RISCVTargetInfo::fillValidTuneCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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llvm::RISCV::fillValidTuneCPUArchList(Values, false);
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}
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bool RISCV64TargetInfo::isValidCPUName(StringRef Name) const {
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return llvm::RISCV::checkCPUKind(llvm::RISCV::parseCPUKind(Name),
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/*Is64Bit=*/true);
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}
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void RISCV64TargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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llvm::RISCV::fillValidCPUArchList(Values, true);
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}
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bool RISCV64TargetInfo::isValidTuneCPUName(StringRef Name) const {
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return llvm::RISCV::checkTuneCPUKind(
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llvm::RISCV::parseTuneCPUKind(Name, true),
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/*Is64Bit=*/true);
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}
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void RISCV64TargetInfo::fillValidTuneCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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llvm::RISCV::fillValidTuneCPUArchList(Values, true);
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bool Is64Bit = getTriple().isArch64Bit();
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llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
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}
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@ -100,6 +100,11 @@ public:
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bool useFP16ConversionIntrinsics() const override {
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return false;
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}
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bool isValidCPUName(StringRef Name) const override;
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool isValidTuneCPUName(StringRef Name) const override;
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void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
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};
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class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
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public:
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@ -119,11 +124,6 @@ public:
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return false;
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}
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bool isValidCPUName(StringRef Name) const override;
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool isValidTuneCPUName(StringRef Name) const override;
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void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
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void setMaxAtomicWidth() override {
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MaxAtomicPromoteWidth = 128;
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@ -148,11 +148,6 @@ public:
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return false;
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}
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bool isValidCPUName(StringRef Name) const override;
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool isValidTuneCPUName(StringRef Name) const override;
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void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
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void setMaxAtomicWidth() override {
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MaxAtomicPromoteWidth = 128;
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