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Move the Blackfin port away from getRegClassForInlineAsmConstraint by 

creating a few specific register classes.

Part of rdar://9643582

llvm-svn: 134086
This commit is contained in:
Eric Christopher 2011-06-29 19:30:29 +00:00
parent d0e48c84f0
commit dabd8a7bef
3 changed files with 22 additions and 29 deletions
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34
llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp
View File

@ -621,39 +621,21 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
case 'w': return Pair(0U, ALLRegisterClass);
case 'Z': return Pair(P3, PRegisterClass);
case 'Y': return Pair(P1, PRegisterClass);
case 'z': return Pair(0U, zConsRegisterClass);
case 'D': return Pair(0U, DConsRegisterClass);
case 'W': return Pair(0U, WConsRegisterClass);
case 'c': return Pair(0U, cConsRegisterClass);
case 't': return Pair(0U, tConsRegisterClass);
case 'u': return Pair(0U, uConsRegisterClass);
case 'k': return Pair(0U, kConsRegisterClass);
case 'y': return Pair(0U, yConsRegisterClass);
}
// Not implemented: q0-q7, qA. Use {R2} etc instead.
// Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to
// getRegClassForInlineAsmConstraint()
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}
std::vector<unsigned> BlackfinTargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
using namespace BF;
if (Constraint.size() != 1)
return std::vector<unsigned>();
switch (Constraint[0]) {
case 'z': return make_vector<unsigned>(P0, P1, P2, 0);
case 'D': return make_vector<unsigned>(R0, R2, R4, R6, 0);
case 'W': return make_vector<unsigned>(R1, R3, R5, R7, 0);
case 'c': return make_vector<unsigned>(I0, I1, I2, I3,
B0, B1, B2, B3,
L0, L1, L2, L3, 0);
case 't': return make_vector<unsigned>(LT0, LT1, 0);
case 'u': return make_vector<unsigned>(LB0, LB1, 0);
case 'k': return make_vector<unsigned>(LC0, LC1, 0);
case 'y': return make_vector<unsigned>(RETS, RETN, RETI, RETX, RETE,
ASTAT, SEQSTAT, USP, 0);
}
return std::vector<unsigned>();
}
bool BlackfinTargetLowering::
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
// The Blackfin target isn't yet aware of offsets.

3
llvm/lib/Target/Blackfin/BlackfinISelLowering.h
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@ -48,9 +48,6 @@ namespace llvm {
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
std::vector<unsigned>
getRegClassForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
const char *getTargetNodeName(unsigned Opcode) const;

14
llvm/lib/Target/Blackfin/BlackfinRegisterInfo.td
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@ -261,3 +261,17 @@ def StatBit : RegisterClass<"BF", [i1], 8,
// Should be i40, but that isn't defined. It is not a legal type yet anyway.
def Accu : RegisterClass<"BF", [i64], 64, (add A0, A1)>;
// Register classes to match inline asm constraints.
def zCons : RegisterClass<"BF", [i32], 32, (add P0, P1, P2)>;
def DCons : RegisterClass<"BF", [i32], 32, (add R0, R2, R4, R6)>;
def WCons : RegisterClass<"BF", [i32], 32, (add R1, R3, R5, R7)>;
def cCons : RegisterClass<"BF", [i32], 32, (add I0, I1, I2, I3,
B0, B1, B2, B3,
L0, L1, L2, L3)>;
def tCons : RegisterClass<"BF", [i32], 32, (add LT0, LT1)>;
def uCons : RegisterClass<"BF", [i32], 32, (add LB0, LB1)>;
def kCons : RegisterClass<"BF", [i32], 32, (add LC0, LC1)>;
def yCons : RegisterClass<"BF", [i32], 32, (add RETS, RETN, RETI, RETX,
RETE, ASTAT, SEQSTAT,
USP)>;