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[ARM] Make testcase more explicit. NFC. 

The q8/d16 thing is silly;  I'd be happy to hear about a better
way to write those tests where simple substitution isn't enough..

llvm-svn: 228258
This commit is contained in:
Ahmed Bougacha 2015-02-05 01:45:28 +00:00
parent 3bd13ca4e1
commit daaf3d9b58
1 changed files with 58 additions and 23 deletions
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81
llvm/test/CodeGen/ARM/big-endian-neon-extend.ll
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@ -2,10 +2,18 @@
define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
; CHECK-LABEL: vector_ext_2i8_to_2i64:
; CHECK: vld1.16 {[[REG:d[0-9]+]]
; CHECK: vmov.i64 {{q[0-9]+}}, #0xff
; CHECK: vrev16.8 [[REG]], [[REG]]
; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]]
; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xff
; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]]
; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
; CHECK-NEXT: bx lr
%1 = load <2 x i8>* %loadaddr
%2 = zext <2 x i8> %1 to <2 x i64>
store <2 x i64> %2, <2 x i64>* %storeaddr
@ -14,10 +22,17 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr
define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
; CHECK-LABEL: vector_ext_2i16_to_2i64:
; CHECK: vld1.32 {[[REG:d[0-9]+]]
; CHECK: vmov.i64 {{q[0-9]+}}, #0xffff
; CHECK: vrev32.16 [[REG]], [[REG]]
; CHECK: vmovl.u16 {{q[0-9]+}}, [[REG]]
; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xffff
; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]]
; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
; CHECK-NEXT: bx lr
%1 = load <2 x i16>* %loadaddr
%2 = zext <2 x i16> %1 to <2 x i64>
store <2 x i64> %2, <2 x i64>* %storeaddr
@ -27,8 +42,13 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd
define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) {
; CHECK-LABEL: vector_ext_2i8_to_2i32:
; CHECK: vld1.16 {[[REG:d[0-9]+]]
; CHECK: vrev16.8 [[REG]], [[REG]]
; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
%1 = load <2 x i8>* %loadaddr
%2 = zext <2 x i8> %1 to <2 x i32>
store <2 x i32> %2, <2 x i32>* %storeaddr
@ -37,9 +57,12 @@ define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr
define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) {
; CHECK-LABEL: vector_ext_2i16_to_2i32:
; CHECK: vld1.32 {[[REG:d[0-9]+]]
; CHECK: vrev32.16 [[REG]], [[REG]]
; CHECK: vmovl.u16 {{q[0-9]+}}, [[REG]]
; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
%1 = load <2 x i16>* %loadaddr
%2 = zext <2 x i16> %1 to <2 x i32>
store <2 x i32> %2, <2 x i32>* %storeaddr
@ -48,9 +71,15 @@ define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeadd
define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) {
; CHECK-LABEL: vector_ext_2i8_to_2i16:
; CHECK: vld1.16 {[[REG:d[0-9]+]]
; CHECK: vrev16.8 [[REG]], [[REG]]
; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]]
; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
; CHECK-NEXT: vuzp.16 [[REG]], d17
; CHECK-NEXT: vrev32.16 [[REG]], d17
; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]
; CHECK-NEXT: bx lr
%1 = load <2 x i8>* %loadaddr
%2 = zext <2 x i8> %1 to <2 x i16>
store <2 x i16> %2, <2 x i16>* %storeaddr
@ -59,9 +88,13 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr
define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) {
; CHECK-LABEL: vector_ext_4i8_to_4i32:
; CHECK: vld1.32 {[[REG:d[0-9]+]]
; CHECK: vrev32.8 [[REG]], [[REG]]
; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]]
; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
; CHECK-NEXT: bx lr
%1 = load <4 x i8>* %loadaddr
%2 = zext <4 x i8> %1 to <4 x i32>
store <4 x i32> %2, <4 x i32>* %storeaddr
@ -70,12 +103,14 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr
define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) {
; CHECK-LABEL: vector_ext_4i8_to_4i16:
; CHECK: vld1.32 {[[REG:d[0-9]+]]
; CHECK: vrev32.8 [[REG]], [[REG]]
; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]]
; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
; CHECK-NEXT: vstr [[REG]], [r1]
; CHECK-NEXT: bx lr
%1 = load <4 x i8>* %loadaddr
%2 = zext <4 x i8> %1 to <4 x i16>
store <4 x i16> %2, <4 x i16>* %storeaddr
ret void
}