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ARM encoding for VSWP got the second operand incorrect. 

Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

llvm-svn: 153766
This commit is contained in:
Jim Grosbach 2012-03-30 18:53:01 +00:00
parent 74005ae691
commit daa04130ed
2 changed files with 11 additions and 4 deletions
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8
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -4787,12 +4787,12 @@ def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
// Vector Swap
def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
(outs DPR:$Vd, DPR:$Vd1), (ins DPR:$Vm, DPR:$Vm1),
NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1",
(outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
[]>;
def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
(outs QPR:$Vd, QPR:$Vd1), (ins QPR:$Vm, QPR:$Vm1),
NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1",
(outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
[]>;
// Vector Move Operations.

7
llvm/test/MC/ARM/neon-vswp.s Normal file
View File

@ -0,0 +1,7 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
vswp d1, d2
vswp q1, q2
@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]