forked from OSchip/llvm-project
[AArch64] Avoid adding duplicate implicit operands when expanding pseudo insts.
When expanding pseudo insts, in order to create a new machine instr, we use BuildMI, which will add implicit operands by default. And transferImpOps will also copy implicit operands from old ones. Finally, duplicate implicit operands are added to the same inst. Sometimes this can cause correctness issues. Like below inst, renamable $w18 = nsw SUBSWrr renamable $w30, renamable $w14, implicit-def dead $nzcv After expanding, it will become $w18 = SUBSWrs renamable $w13, renamable $w14, 0, implicit-def $nzcv, implicit-def dead $nzcv A redundant implicit-def $nzcv is added, but the dead flag is missing. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D109069
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@ -937,12 +937,16 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
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case AArch64::ORRWrr: Opcode = AArch64::ORRWrs; break;
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case AArch64::ORRXrr: Opcode = AArch64::ORRXrs; break;
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}
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MachineInstrBuilder MIB1 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
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MI.getOperand(0).getReg())
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.add(MI.getOperand(1))
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.add(MI.getOperand(2))
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
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MachineFunction &MF = *MBB.getParent();
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// Try to create new inst without implicit operands added.
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MachineInstr *NewMI = MF.CreateMachineInstr(
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TII->get(Opcode), MI.getDebugLoc(), /*NoImplicit=*/true);
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MBB.insert(MBBI, NewMI);
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MachineInstrBuilder MIB1(MF, NewMI);
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MIB1.addReg(MI.getOperand(0).getReg(), RegState::Define)
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.add(MI.getOperand(1))
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.add(MI.getOperand(2))
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
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transferImpOps(MI, MIB1, MIB1);
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MI.eraseFromParent();
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return true;
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@ -0,0 +1,21 @@
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# RUN: llc -run-pass=aarch64-expand-pseudo -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck %s
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---
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# CHECK-LABEL: name: test
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# CHECK-LABEL: bb.0:
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# CHECK: $w5 = SUBSWrs renamable $w3, renamable $w2, 0, implicit-def dead $nzcv
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# CHECK-NEXT: $w6 = SUBSWrs renamable $w5, renamable $w3, 0, implicit-def $nzcv
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# CHECK-NEXT: RET undef $lr
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#
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name: test
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alignment: 4
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w5, $w6, $x2, $x3
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renamable $w5 = nsw SUBSWrr renamable $w3, renamable $w2, implicit-def dead $nzcv
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renamable $w6 = nsw SUBSWrr renamable $w5, renamable $w3, implicit-def $nzcv
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RET_ReallyLR
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...
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