forked from OSchip/llvm-project
Temporarily Revert "[X86][SSE] Simplify vector LOAD + EXTEND on
pre-SSE41 hardware" as it seems to be causing crashes during code generation in halide. PR forthcoming. This reverts commit r263303. llvm-svn: 263512
This commit is contained in:
Eric Christopher
parent
abde7dfbe9
commit
da8b3f1914
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@ -653,7 +653,6 @@ private:
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void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
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@ -621,12 +621,6 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
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break;
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case ISD::ANY_EXTEND_VECTOR_INREG:
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case ISD::SIGN_EXTEND_VECTOR_INREG:
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case ISD::ZERO_EXTEND_VECTOR_INREG:
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SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
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break;
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case ISD::BITREVERSE:
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case ISD::BSWAP:
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case ISD::CONVERT_RNDSAT:
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@ -923,39 +917,6 @@ void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
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DAG.getValueType(HiVT));
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}
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void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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unsigned Opcode = N->getOpcode();
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SDValue N0 = N->getOperand(0);
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SDLoc dl(N);
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SDValue InLo, InHi;
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GetSplitVector(N0, InLo, InHi);
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EVT InLoVT = InLo.getValueType();
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unsigned InNumElements = InLoVT.getVectorNumElements();
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EVT OutLoVT, OutHiVT;
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std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
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unsigned OutNumElements = OutLoVT.getVectorNumElements();
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assert((2 * OutNumElements) <= InNumElements &&
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"Illegal extend vector in reg split");
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// *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
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// input vector (i.e. we only use InLo):
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// OutLo will extend the first OutNumElements from InLo.
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// OutHi will extend the next OutNumElements from InLo.
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// Shuffle the elements from InLo for OutHi into the bottom elements to
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// create a 'fake' InHi.
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SmallVector<int, 8> SplitHi(InNumElements, -1);
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for (unsigned i = 0; i != OutNumElements; ++i)
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SplitHi[i] = i + OutNumElements;
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InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
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Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
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Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
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}
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void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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SDValue Vec = N->getOperand(0);
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@ -28585,9 +28585,7 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG,
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// If target-size is 128-bits (or 256-bits on AVX2 target), then convert to
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// ISD::*_EXTEND_VECTOR_INREG which ensures lowering to X86ISD::V*EXT.
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// Also use this if we don't have SSE41 to allow the legalizer do its job.
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if (!Subtarget.hasSSE41() || VT.is128BitVector() ||
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(VT.is256BitVector() && Subtarget.hasInt256())) {
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if (VT.is128BitVector() || (VT.is256BitVector() && Subtarget.hasInt256())) {
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SDValue ExOp = ExtendVecSize(DL, N0, VT.getSizeInBits());
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return Opcode == ISD::SIGN_EXTEND
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? DAG.getSignExtendVectorInReg(ExOp, DL, VT)
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@ -544,20 +544,23 @@ define <4 x i64> @load_zext_4i8_to_4i64(<4 x i8> *%ptr) {
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; SSE2-LABEL: load_zext_4i8_to_4i64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
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; SSE2-NEXT: pand %xmm2, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_zext_4i8_to_4i64:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
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; SSSE3-NEXT: movdqa %xmm1, %xmm0
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[2],zero,zero,zero,zero,zero,zero,zero,xmm1[3],zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[4],zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[8],zero,zero,zero,zero,zero,zero,zero,xmm1[12],zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_zext_4i8_to_4i64:
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@ -622,21 +625,22 @@ define <8 x i32> @load_zext_8i8_to_8i32(<8 x i8> *%ptr) {
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; SSE2-LABEL: load_zext_8i8_to_8i32:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; SSE2-NEXT: pand %xmm2, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_zext_8i8_to_8i32:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; SSSE3-NEXT: pxor %xmm2, %xmm2
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; SSSE3-NEXT: movdqa %xmm1, %xmm0
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
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; SSSE3-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[6],zero,zero,zero
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[8],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[14],zero,zero,zero
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_zext_8i8_to_8i32:
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@ -670,33 +674,34 @@ entry:
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define <8 x i64> @load_zext_8i8_to_8i64(<8 x i8> *%ptr) {
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; SSE2-LABEL: load_zext_8i8_to_8i64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; SSE2-NEXT: pxor %xmm4, %xmm4
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3]
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
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; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm4[2],xmm1[3],xmm4[3]
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3],xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3]
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; SSE2-NEXT: movdqa %xmm3, %xmm2
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; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
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; SSE2-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm4[2],xmm3[3],xmm4[3]
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; SSE2-NEXT: movq {{.*#+}} xmm3 = mem[0],zero
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,1,0,3]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7]
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; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
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; SSE2-NEXT: pand %xmm4, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,1,3]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,5,5,6,7]
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; SSE2-NEXT: pand %xmm4, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,1,2,3]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,5,5,6,7]
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; SSE2-NEXT: pand %xmm4, %xmm2
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[3,1,3,3]
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; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,5,5,6,7]
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; SSE2-NEXT: pand %xmm4, %xmm3
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_zext_8i8_to_8i64:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [0,128,128,128,128,128,128,128,1,128,128,128,128,128,128,128]
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; SSSE3-NEXT: movdqa %xmm1, %xmm0
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; SSSE3-NEXT: pshufb %xmm4, %xmm0
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; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [2,128,128,128,128,128,128,128,3,128,128,128,128,128,128,128]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,3]
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; SSSE3-NEXT: pshufb %xmm5, %xmm1
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; SSSE3-NEXT: movq {{.*#+}} xmm3 = mem[0],zero
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
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; SSSE3-NEXT: movdqa %xmm3, %xmm0
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[2],zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: movdqa %xmm3, %xmm1
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[4],zero,zero,zero,zero,zero,zero,zero,xmm1[6],zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: movdqa %xmm3, %xmm2
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; SSSE3-NEXT: pshufb %xmm4, %xmm2
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; SSSE3-NEXT: pshufb %xmm5, %xmm3
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; SSSE3-NEXT: pshufb {{.*#+}} xmm2 = xmm2[8],zero,zero,zero,zero,zero,zero,zero,xmm2[10],zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: pshufb {{.*#+}} xmm3 = xmm3[12],zero,zero,zero,zero,zero,zero,zero,xmm3[14],zero,zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_zext_8i8_to_8i64:
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@ -846,21 +851,21 @@ define <4 x i64> @load_zext_4i16_to_4i64(<4 x i16> *%ptr) {
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; SSE2-LABEL: load_zext_4i16_to_4i64:
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; SSE2: # BB#0: # %entry
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; SSE2-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0,65535,0,0,0]
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
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; SSE2-NEXT: pand %xmm2, %xmm1
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_zext_4i16_to_4i64:
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; SSSE3: # BB#0: # %entry
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; SSSE3-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; SSSE3-NEXT: pxor %xmm2, %xmm2
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
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; SSSE3-NEXT: movdqa %xmm1, %xmm0
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; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSSE3-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,zero,zero,zero,zero,zero,xmm0[4,5],zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[8,9],zero,zero,zero,zero,zero,zero,xmm1[12,13],zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_zext_4i16_to_4i64:
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|
|
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Loading…
Reference in New Issue