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ARM: preserve undef flag in pseudo instruction expanders 

Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.

llvm-svn: 191961
This commit is contained in:
Matthias Braun 2013-10-04 16:52:51 +00:00
parent db3c60e388
commit da621165ca
2 changed files with 21 additions and 19 deletions
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33
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -692,10 +692,9 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
MI.getOperand(1).getReg())
.addReg(MI.getOperand(2).getReg(),
getKillRegState(MI.getOperand(2).isKill()))
.addOperand(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg());
.addOperand(MI.getOperand(4));
MI.eraseFromParent();
return true;
@ -705,10 +704,9 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
MI.getOperand(1).getReg())
.addReg(MI.getOperand(2).getReg(),
getKillRegState(MI.getOperand(2).isKill()))
.addOperand(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg())
.addOperand(MI.getOperand(4))
.addReg(0); // 's' bit
MI.eraseFromParent();
@ -717,11 +715,10 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
case ARM::MOVCCsi: {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
(MI.getOperand(1).getReg()))
.addReg(MI.getOperand(2).getReg(),
getKillRegState(MI.getOperand(2).isKill()))
.addOperand(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm())
.addImm(MI.getOperand(4).getImm()) // 'pred'
.addReg(MI.getOperand(5).getReg())
.addOperand(MI.getOperand(5))
.addReg(0); // 's' bit
MI.eraseFromParent();
@ -730,13 +727,11 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
case ARM::MOVCCsr: {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
(MI.getOperand(1).getReg()))
.addReg(MI.getOperand(2).getReg(),
getKillRegState(MI.getOperand(2).isKill()))
.addReg(MI.getOperand(3).getReg(),
getKillRegState(MI.getOperand(3).isKill()))
.addOperand(MI.getOperand(2))
.addOperand(MI.getOperand(3))
.addImm(MI.getOperand(4).getImm())
.addImm(MI.getOperand(5).getImm()) // 'pred'
.addReg(MI.getOperand(6).getReg())
.addOperand(MI.getOperand(6))
.addReg(0); // 's' bit
MI.eraseFromParent();
@ -749,7 +744,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.getOperand(1).getReg())
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg());
.addOperand(MI.getOperand(4));
MI.eraseFromParent();
return true;
}
@ -760,7 +755,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.getOperand(1).getReg())
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg())
.addOperand(MI.getOperand(4))
.addReg(0); // 's' bit
MI.eraseFromParent();
@ -773,7 +768,7 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.getOperand(1).getReg())
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg())
.addOperand(MI.getOperand(4))
.addReg(0); // 's' bit
MI.eraseFromParent();
@ -793,10 +788,10 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
}
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
MI.getOperand(1).getReg())
.addReg(MI.getOperand(2).getReg())
.addOperand(MI.getOperand(2))
.addImm(MI.getOperand(3).getImm())
.addImm(MI.getOperand(4).getImm()) // 'pred'
.addReg(MI.getOperand(5).getReg())
.addOperand(MI.getOperand(5))
.addReg(0); // 's' bit
MI.eraseFromParent();
return true;

7
llvm/test/CodeGen/ARM/select-undef.ll Normal file
View File

@ -0,0 +1,7 @@
; RUN: llc < %s -march=arm -mcpu=swift -verify-machineinstrs
define i32 @func(i32 %arg0, i32 %arg1) {
entry:
%cmp = icmp slt i32 %arg0, 10
%v = select i1 %cmp, i32 undef, i32 %arg1
ret i32 %v
}