forked from OSchip/llvm-project
AMDGPU/SI: Turn off GPR Indexing Mode immediately after the interested instruction.
Summary: In the current implementation of GPR Indexing Mode when the index is of non-uniform, the s_set_gpr_idx_off instruction is incorrectly inserted after the loop. This will lead the instructions with vgpr operands (v_readfirstlane for example) to read incorrect vgpr. In this patch, we fix the issue by inserting s_set_gpr_idx_on/off immediately around the interested instruction. Reviewers: rampitec Differential Revision: https://reviews.llvm.org/D43297 llvm-svn: 325355
This commit is contained in:
Changpeng Fang
parent
ff53a4a234
commit
da38b5fd49
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@ -2744,7 +2744,8 @@ static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
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unsigned PhiReg,
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unsigned InitSaveExecReg,
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int Offset,
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bool UseGPRIdxMode) {
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bool UseGPRIdxMode,
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bool IsIndirectSrc) {
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MachineBasicBlock::iterator I = LoopBB.begin();
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unsigned PhiExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
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@ -2773,6 +2774,12 @@ static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
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.addReg(CurrentIdxReg)
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.addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
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// Update EXEC, save the original EXEC value to VCC.
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BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), NewExec)
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.addReg(CondReg, RegState::Kill);
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MRI.setSimpleHint(NewExec, CondReg);
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if (UseGPRIdxMode) {
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unsigned IdxReg;
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if (Offset == 0) {
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@ -2783,11 +2790,13 @@ static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
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.addReg(CurrentIdxReg, RegState::Kill)
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.addImm(Offset);
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}
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MachineInstr *SetIdx =
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BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_IDX))
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.addReg(IdxReg, RegState::Kill);
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SetIdx->getOperand(2).setIsUndef();
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unsigned IdxMode = IsIndirectSrc ?
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VGPRIndexMode::SRC0_ENABLE : VGPRIndexMode::DST_ENABLE;
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MachineInstr *SetOn =
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BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
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.addReg(IdxReg, RegState::Kill)
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.addImm(IdxMode);
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SetOn->getOperand(3).setIsUndef();
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} else {
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// Move index from VCC into M0
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if (Offset == 0) {
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@ -2800,12 +2809,6 @@ static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
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}
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}
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// Update EXEC, save the original EXEC value to VCC.
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BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), NewExec)
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.addReg(CondReg, RegState::Kill);
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MRI.setSimpleHint(NewExec, CondReg);
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// Update EXEC, switch all done bits to 0 and all todo bits to 1.
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MachineInstr *InsertPt =
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BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
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@ -2833,7 +2836,8 @@ static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII,
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unsigned InitResultReg,
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unsigned PhiReg,
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int Offset,
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bool UseGPRIdxMode) {
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bool UseGPRIdxMode,
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bool IsIndirectSrc) {
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MachineFunction *MF = MBB.getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const DebugLoc &DL = MI.getDebugLoc();
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@ -2872,7 +2876,7 @@ static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII,
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auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
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InitResultReg, DstReg, PhiReg, TmpExec,
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Offset, UseGPRIdxMode);
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Offset, UseGPRIdxMode, IsIndirectSrc);
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MachineBasicBlock::iterator First = RemainderBB->begin();
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BuildMI(*RemainderBB, First, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
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@ -3007,17 +3011,8 @@ static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
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BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
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if (UseGPRIdxMode) {
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MachineInstr *SetOn = BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
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.addImm(0) // Reset inside loop.
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.addImm(VGPRIndexMode::SRC0_ENABLE);
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SetOn->getOperand(3).setIsUndef();
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// Disable again after the loop.
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BuildMI(MBB, std::next(I), DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
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}
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auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, UseGPRIdxMode);
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auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg,
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Offset, UseGPRIdxMode, true);
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MachineBasicBlock *LoopBB = InsPt->getParent();
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if (UseGPRIdxMode) {
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@ -3025,6 +3020,7 @@ static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
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.addReg(SrcReg, RegState::Undef, SubReg)
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.addReg(SrcReg, RegState::Implicit)
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.addReg(AMDGPU::M0, RegState::Implicit);
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BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
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} else {
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BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
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.addReg(SrcReg, RegState::Undef, SubReg)
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@ -3125,22 +3121,10 @@ static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
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const DebugLoc &DL = MI.getDebugLoc();
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if (UseGPRIdxMode) {
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MachineBasicBlock::iterator I(&MI);
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MachineInstr *SetOn = BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
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.addImm(0) // Reset inside loop.
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.addImm(VGPRIndexMode::DST_ENABLE);
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SetOn->getOperand(3).setIsUndef();
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// Disable again after the loop.
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BuildMI(MBB, std::next(I), DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
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}
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unsigned PhiReg = MRI.createVirtualRegister(VecRC);
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auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
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Offset, UseGPRIdxMode);
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Offset, UseGPRIdxMode, false);
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MachineBasicBlock *LoopBB = InsPt->getParent();
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if (UseGPRIdxMode) {
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@ -3150,6 +3134,7 @@ static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
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.addReg(Dst, RegState::ImplicitDefine)
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.addReg(PhiReg, RegState::Implicit)
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.addReg(AMDGPU::M0, RegState::Implicit);
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BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
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} else {
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const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
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@ -118,23 +118,21 @@ entry:
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; The offset depends on the register that holds the first element of the vector.
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; FIXME: The waitcnt for the argument load can go after the loop
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; IDXMODE: s_set_gpr_idx_on 0, src0
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; GCN: s_mov_b64 s{{\[[0-9]+:[0-9]+\]}}, exec
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; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]:
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; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]], v{{[0-9]+}}
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_add_i32 m0, [[READLANE]], 0xfffffe0
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; MOVREL: s_and_saveexec_b64 vcc, vcc
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; MOVREL: v_movrels_b32_e32 [[RESULT:v[0-9]+]], v1
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; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00
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; IDXMODE: s_set_gpr_idx_idx [[ADD_IDX]]
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; IDXMODE: s_and_saveexec_b64 vcc, vcc
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; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], src0
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; IDXMODE: v_mov_b32_e32 [[RESULT:v[0-9]+]], v1
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; IDXMODE: s_set_gpr_idx_off
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; GCN: s_cbranch_execnz
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; IDXMODE: s_set_gpr_idx_off
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @extract_neg_offset_vgpr(i32 addrspace(1)* %out) {
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entry:
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@ -250,21 +248,19 @@ entry:
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; GCN: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
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; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]:
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; GCN: v_readfirstlane_b32 [[READLANE:s[0-9]+]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_add_i32 m0, [[READLANE]], 0xfffffe00
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; MOVREL: s_and_saveexec_b64 vcc, vcc
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; MOVREL: v_movreld_b32_e32 [[VEC_ELT0]], 5
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; IDXMODE: s_addk_i32 [[ADD_IDX:s[0-9]+]], 0xfe00{{$}}
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; IDXMODE: s_set_gpr_idx_idx [[ADD_IDX]]
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; IDXMODE: s_and_saveexec_b64 vcc, vcc
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; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst
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; IDXMODE: v_mov_b32_e32 v{{[0-9]+}}, 5
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; IDXMODE: s_set_gpr_idx_off
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; GCN: s_cbranch_execnz [[LOOPBB]]
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; GCN: s_mov_b64 exec, [[SAVEEXEC]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN: buffer_store_dword
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define amdgpu_kernel void @insert_neg_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
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entry:
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@ -283,8 +279,6 @@ entry:
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; GCN-DAG: v_mov_b32_e32 [[VEC_ELT3:v[0-9]+]], 4{{$}}
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; GCN-DAG: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x1f4{{$}}
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; IDXMODE: s_set_gpr_idx_on 0, dst
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; GCN: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
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; The offset depends on the register that holds the first element of the vector.
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@ -294,12 +288,11 @@ entry:
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; MOVREL: v_movreld_b32_e32 [[VEC_ELT0]], [[VAL]]
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; IDXMODE: s_add_i32 [[ADD_IDX:s[0-9]+]], [[READLANE]], -16
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; IDXMODE: s_set_gpr_idx_idx [[ADD_IDX]]
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; IDXMODE: s_set_gpr_idx_on [[ADD_IDX]], dst
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; IDXMODE: v_mov_b32_e32 [[VEC_ELT0]], [[VAL]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN: s_cbranch_execnz
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; IDXMODE: s_set_gpr_idx_off
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define amdgpu_kernel void @insert_neg_inline_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
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entry:
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%id = call i32 @llvm.amdgcn.workitem.id.x() #1
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@ -322,52 +315,46 @@ entry:
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; GCN-DAG: v_mov_b32_e32 [[VEC_ELT0:v[0-9]+]], [[S_ELT0]]
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; GCN-DAG: v_mov_b32_e32 [[VEC_ELT1:v[0-9]+]], [[S_ELT1]]
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; IDXMODE: s_set_gpr_idx_on 0, src0
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; GCN: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec
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; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_mov_b32 m0, [[READLANE]]
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; MOVREL: s_and_saveexec_b64 vcc, vcc
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; MOVREL: v_movrels_b32_e32 [[MOVREL0:v[0-9]+]], [[VEC_ELT0]]
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; IDXMODE: s_set_gpr_idx_idx [[READLANE]]
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; IDXMODE: s_and_saveexec_b64 vcc, vcc
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; IDXMODE: s_set_gpr_idx_on [[READLANE]], src0
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; IDXMODE: v_mov_b32_e32 [[MOVREL0:v[0-9]+]], [[VEC_ELT0]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN-NEXT: s_xor_b64 exec, exec, vcc
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; GCN-NEXT: s_cbranch_execnz [[LOOP0]]
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; FIXME: Redundant copy
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; GCN: s_mov_b64 exec, [[MASK]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN: v_mov_b32_e32 [[VEC_ELT1_2:v[0-9]+]], [[S_ELT1]]
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; IDXMODE: s_set_gpr_idx_on 0, src0
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; GCN: s_mov_b64 [[MASK2:s\[[0-9]+:[0-9]+\]]], exec
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; GCN: [[LOOP1:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_mov_b32 m0, [[READLANE]]
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; MOVREL: s_and_saveexec_b64 vcc, vcc
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; MOVREL-NEXT: v_movrels_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT1_2]]
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; IDXMODE: s_set_gpr_idx_idx [[READLANE]]
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; IDXMODE: s_and_saveexec_b64 vcc, vcc
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; IDXMODE: s_set_gpr_idx_on [[READLANE]], src0
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; IDXMODE-NEXT: v_mov_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT1_2]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN-NEXT: s_xor_b64 exec, exec, vcc
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; GCN: s_cbranch_execnz [[LOOP1]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN: buffer_store_dword [[MOVREL0]]
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; GCN: buffer_store_dword [[MOVREL1]]
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define amdgpu_kernel void @extract_vgpr_offset_multiple_in_block(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) #0 {
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@ -403,42 +390,38 @@ bb2:
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; GCN: v_mov_b32_e32 v[[VEC_ELT1:[0-9]+]], s{{[0-9]+}}
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; GCN: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]
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; IDXMODE: s_set_gpr_idx_on 0, dst
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; GCN: [[LOOP0:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_mov_b32 m0, [[READLANE]]
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; MOVREL: s_and_saveexec_b64 vcc, vcc
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; MOVREL-NEXT: v_movreld_b32_e32 v[[VEC_ELT0]], [[INS0]]
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; IDXMODE: s_set_gpr_idx_idx [[READLANE]]
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; IDXMODE: s_and_saveexec_b64 vcc, vcc
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; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst
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; IDXMODE-NEXT: v_mov_b32_e32 v[[VEC_ELT0]], [[INS0]]
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; IDXMODE: s_set_gpr_idx_off
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; GCN-NEXT: s_xor_b64 exec, exec, vcc
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; GCN: s_cbranch_execnz [[LOOP0]]
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; FIXME: Redundant copy
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; GCN: s_mov_b64 exec, [[MASK:s\[[0-9]+:[0-9]+\]]]
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; IDXMODE: s_set_gpr_idx_off
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; IDXMODE: s_set_gpr_idx_on 0, dst
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; GCN: s_mov_b64 [[MASK]], exec
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; GCN: [[LOOP1:BB[0-9]+_[0-9]+]]:
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; GCN-NEXT: v_readfirstlane_b32 [[READLANE:s[0-9]+]], [[IDX0]]
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; GCN: v_cmp_eq_u32_e32 vcc, [[READLANE]], [[IDX0]]
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; GCN: s_and_saveexec_b64 vcc, vcc
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; MOVREL: s_mov_b32 m0, [[READLANE]]
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; MOVREL: s_and_saveexec_b64 vcc, vcc
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; MOVREL-NEXT: v_movreld_b32_e32 v[[VEC_ELT1]], 63
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; IDXMODE: s_set_gpr_idx_idx [[READLANE]]
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; IDXMODE: s_and_saveexec_b64 vcc, vcc
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; IDXMODE: s_set_gpr_idx_on [[READLANE]], dst
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; IDXMODE-NEXT: v_mov_b32_e32 v[[VEC_ELT1]], 63
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; IDXMODE: s_set_gpr_idx_off
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; GCN-NEXT: s_xor_b64 exec, exec, vcc
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; GCN: s_cbranch_execnz [[LOOP1]]
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@ -639,7 +622,6 @@ define amdgpu_kernel void @insertelement_v4f32_or_index(<4 x float> addrspace(1)
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; GCN: {{^BB[0-9]+_[0-9]+}}:
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; GCN: s_mov_b64 exec,
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; IDXMODE: s_set_gpr_idx_off
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; GCN: [[BB2]]:
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; GCN: v_cmp_le_i32_e32 vcc, s{{[0-9]+}}, [[PHIREG]]
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@ -648,8 +630,10 @@ define amdgpu_kernel void @insertelement_v4f32_or_index(<4 x float> addrspace(1)
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; GCN: [[REGLOOP:BB[0-9]+_[0-9]+]]:
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; MOVREL: v_movreld_b32_e32
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; IDXMODE: s_set_gpr_idx_idx
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; IDXMODE: s_set_gpr_idx_on
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; IDXMODE: v_mov_b32_e32
|
||||
; IDXMODE: s_set_gpr_idx_off
|
||||
|
||||
; GCN: s_cbranch_execnz [[REGLOOP]]
|
||||
define amdgpu_kernel void @broken_phi_bb(i32 %arg, i32 %arg1) #0 {
|
||||
bb:
|
||||
|
|
|
|||
Loading…
Reference in New Issue