forked from OSchip/llvm-project
[SLP] allow matching integer min/max intrinsics as reduction ops
This is a 2nd try of:3c8473ba53which was reverted at:a26312f9d4because of crashing. This version includes extra code and tests to avoid the known crashing examples as discussed in PR49730. Original commit message: As noted in D98152, we need to patch SLP to avoid regressions when we start canonicalizing to integer min/max intrinsics. Most of the real work to make this possible was in:7202f47508Differential Revision: https://reviews.llvm.org/D98981
This commit is contained in:
Sanjay Patel
parent
dcf96178cb
commit
da381cf7ce
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@ -6570,7 +6570,7 @@ class HorizontalReduction {
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/// Creates reduction operation with the current opcode.
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static Value *createOp(IRBuilder<> &Builder, RecurKind Kind, Value *LHS,
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Value *RHS, const Twine &Name) {
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Value *RHS, const Twine &Name, bool UseSelect) {
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unsigned RdxOpcode = RecurrenceDescriptor::getOpcode(Kind);
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switch (Kind) {
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case RecurKind::Add:
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@ -6586,23 +6586,30 @@ class HorizontalReduction {
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return Builder.CreateBinaryIntrinsic(Intrinsic::maxnum, LHS, RHS);
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case RecurKind::FMin:
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return Builder.CreateBinaryIntrinsic(Intrinsic::minnum, LHS, RHS);
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case RecurKind::SMax: {
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case RecurKind::SMax:
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if (UseSelect) {
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Value *Cmp = Builder.CreateICmpSGT(LHS, RHS, Name);
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return Builder.CreateSelect(Cmp, LHS, RHS, Name);
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}
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case RecurKind::SMin: {
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return Builder.CreateBinaryIntrinsic(Intrinsic::smax, LHS, RHS);
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case RecurKind::SMin:
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if (UseSelect) {
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Value *Cmp = Builder.CreateICmpSLT(LHS, RHS, Name);
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return Builder.CreateSelect(Cmp, LHS, RHS, Name);
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}
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case RecurKind::UMax: {
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return Builder.CreateBinaryIntrinsic(Intrinsic::smin, LHS, RHS);
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case RecurKind::UMax:
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if (UseSelect) {
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Value *Cmp = Builder.CreateICmpUGT(LHS, RHS, Name);
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return Builder.CreateSelect(Cmp, LHS, RHS, Name);
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}
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case RecurKind::UMin: {
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return Builder.CreateBinaryIntrinsic(Intrinsic::umax, LHS, RHS);
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case RecurKind::UMin:
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if (UseSelect) {
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Value *Cmp = Builder.CreateICmpULT(LHS, RHS, Name);
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return Builder.CreateSelect(Cmp, LHS, RHS, Name);
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}
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return Builder.CreateBinaryIntrinsic(Intrinsic::umin, LHS, RHS);
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default:
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llvm_unreachable("Unknown reduction operation.");
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}
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@ -6613,13 +6620,17 @@ class HorizontalReduction {
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static Value *createOp(IRBuilder<> &Builder, RecurKind RdxKind, Value *LHS,
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Value *RHS, const Twine &Name,
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const ReductionOpsListType &ReductionOps) {
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Value *Op = createOp(Builder, RdxKind, LHS, RHS, Name);
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bool UseSelect = ReductionOps.size() == 2;
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assert((!UseSelect || isa<SelectInst>(ReductionOps[1][0])) &&
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"Expected cmp + select pairs for reduction");
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Value *Op = createOp(Builder, RdxKind, LHS, RHS, Name, UseSelect);
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if (RecurrenceDescriptor::isIntMinMaxRecurrenceKind(RdxKind)) {
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if (auto *Sel = dyn_cast<SelectInst>(Op))
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if (auto *Sel = dyn_cast<SelectInst>(Op)) {
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propagateIRFlags(Sel->getCondition(), ReductionOps[0]);
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propagateIRFlags(Op, ReductionOps[1]);
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return Op;
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}
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}
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propagateIRFlags(Op, ReductionOps[0]);
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return Op;
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}
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@ -6627,10 +6638,10 @@ class HorizontalReduction {
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/// from \p I.
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static Value *createOp(IRBuilder<> &Builder, RecurKind RdxKind, Value *LHS,
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Value *RHS, const Twine &Name, Instruction *I) {
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Value *Op = createOp(Builder, RdxKind, LHS, RHS, Name);
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auto *SelI = dyn_cast<SelectInst>(I);
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Value *Op = createOp(Builder, RdxKind, LHS, RHS, Name, SelI != nullptr);
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if (RecurrenceDescriptor::isIntMinMaxRecurrenceKind(RdxKind)) {
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if (auto *Sel = dyn_cast<SelectInst>(Op))
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if (auto *SelI = dyn_cast<SelectInst>(I))
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propagateIRFlags(Sel->getCondition(), SelI->getCondition());
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}
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propagateIRFlags(Op, I);
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@ -6660,9 +6671,10 @@ class HorizontalReduction {
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if (match(I, m_Intrinsic<Intrinsic::minnum>(m_Value(), m_Value())))
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return RecurKind::FMin;
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if (auto *Select = dyn_cast<SelectInst>(I)) {
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// These would also match llvm.{u,s}{min,max} intrinsic call
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// if were not guarded by the SelectInst check above.
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// This matches either cmp+select or intrinsics. SLP is expected to handle
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// either form.
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// TODO: If we are canonicalizing to intrinsics, we can remove several
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// special-case paths that deal with selects.
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if (match(I, m_SMax(m_Value(), m_Value())))
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return RecurKind::SMax;
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if (match(I, m_SMin(m_Value(), m_Value())))
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@ -6671,6 +6683,8 @@ class HorizontalReduction {
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return RecurKind::UMax;
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if (match(I, m_UMin(m_Value(), m_Value())))
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return RecurKind::UMin;
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if (auto *Select = dyn_cast<SelectInst>(I)) {
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// Try harder: look for min/max pattern based on instructions producing
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// same values such as: select ((cmp Inst1, Inst2), Inst1, Inst2).
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// During the intermediate stages of SLP, it's very common to have
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@ -7384,6 +7398,14 @@ static bool matchRdxBop(Instruction *I, Value *&V0, Value *&V1) {
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return true;
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if (match(I, m_Intrinsic<Intrinsic::minnum>(m_Value(V0), m_Value(V1))))
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return true;
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if (match(I, m_Intrinsic<Intrinsic::smax>(m_Value(V0), m_Value(V1))))
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return true;
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if (match(I, m_Intrinsic<Intrinsic::smin>(m_Value(V0), m_Value(V1))))
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return true;
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if (match(I, m_Intrinsic<Intrinsic::umax>(m_Value(V0), m_Value(V1))))
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return true;
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if (match(I, m_Intrinsic<Intrinsic::umin>(m_Value(V0), m_Value(V1))))
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return true;
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return false;
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}
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@ -1018,22 +1018,10 @@ define i32 @smax_intrinsic_rdx_v8i32(i32* %p0) {
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; CHECK-NEXT: [[P5:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 5
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; CHECK-NEXT: [[P6:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 6
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; CHECK-NEXT: [[P7:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 7
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; CHECK-NEXT: [[T0:%.*]] = load i32, i32* [[P0]], align 4
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; CHECK-NEXT: [[T1:%.*]] = load i32, i32* [[P1]], align 4
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; CHECK-NEXT: [[T2:%.*]] = load i32, i32* [[P2]], align 4
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; CHECK-NEXT: [[T3:%.*]] = load i32, i32* [[P3]], align 4
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; CHECK-NEXT: [[T4:%.*]] = load i32, i32* [[P4]], align 4
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; CHECK-NEXT: [[T5:%.*]] = load i32, i32* [[P5]], align 4
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; CHECK-NEXT: [[T6:%.*]] = load i32, i32* [[P6]], align 4
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; CHECK-NEXT: [[T7:%.*]] = load i32, i32* [[P7]], align 4
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; CHECK-NEXT: [[M10:%.*]] = tail call i32 @llvm.smax.i32(i32 [[T1]], i32 [[T0]])
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; CHECK-NEXT: [[M32:%.*]] = tail call i32 @llvm.smax.i32(i32 [[T3]], i32 [[T2]])
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; CHECK-NEXT: [[M54:%.*]] = tail call i32 @llvm.smax.i32(i32 [[T5]], i32 [[T4]])
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; CHECK-NEXT: [[M76:%.*]] = tail call i32 @llvm.smax.i32(i32 [[T7]], i32 [[T6]])
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; CHECK-NEXT: [[M3210:%.*]] = tail call i32 @llvm.smax.i32(i32 [[M32]], i32 [[M10]])
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; CHECK-NEXT: [[M7654:%.*]] = tail call i32 @llvm.smax.i32(i32 [[M76]], i32 [[M54]])
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; CHECK-NEXT: [[M:%.*]] = tail call i32 @llvm.smax.i32(i32 [[M7654]], i32 [[M3210]])
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; CHECK-NEXT: ret i32 [[M]]
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[P0]] to <8 x i32>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP2]])
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%p1 = getelementptr inbounds i32, i32* %p0, i64 1
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%p2 = getelementptr inbounds i32, i32* %p0, i64 2
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@ -1069,22 +1057,10 @@ define i16 @smin_intrinsic_rdx_v8i16(i16* %p0) {
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; CHECK-NEXT: [[P5:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 5
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; CHECK-NEXT: [[P6:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 6
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; CHECK-NEXT: [[P7:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 7
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; CHECK-NEXT: [[T0:%.*]] = load i16, i16* [[P0]], align 4
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; CHECK-NEXT: [[T1:%.*]] = load i16, i16* [[P1]], align 4
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; CHECK-NEXT: [[T2:%.*]] = load i16, i16* [[P2]], align 4
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; CHECK-NEXT: [[T3:%.*]] = load i16, i16* [[P3]], align 4
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; CHECK-NEXT: [[T4:%.*]] = load i16, i16* [[P4]], align 4
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; CHECK-NEXT: [[T5:%.*]] = load i16, i16* [[P5]], align 4
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; CHECK-NEXT: [[T6:%.*]] = load i16, i16* [[P6]], align 4
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; CHECK-NEXT: [[T7:%.*]] = load i16, i16* [[P7]], align 4
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; CHECK-NEXT: [[M10:%.*]] = tail call i16 @llvm.smin.i16(i16 [[T1]], i16 [[T0]])
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; CHECK-NEXT: [[M32:%.*]] = tail call i16 @llvm.smin.i16(i16 [[T3]], i16 [[T2]])
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; CHECK-NEXT: [[M54:%.*]] = tail call i16 @llvm.smin.i16(i16 [[T5]], i16 [[T4]])
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; CHECK-NEXT: [[M76:%.*]] = tail call i16 @llvm.smin.i16(i16 [[T7]], i16 [[T6]])
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; CHECK-NEXT: [[M3210:%.*]] = tail call i16 @llvm.smin.i16(i16 [[M32]], i16 [[M10]])
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; CHECK-NEXT: [[M7654:%.*]] = tail call i16 @llvm.smin.i16(i16 [[M76]], i16 [[M54]])
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; CHECK-NEXT: [[M:%.*]] = tail call i16 @llvm.smin.i16(i16 [[M7654]], i16 [[M3210]])
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; CHECK-NEXT: ret i16 [[M]]
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i16* [[P0]] to <8 x i16>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> [[TMP2]])
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; CHECK-NEXT: ret i16 [[TMP3]]
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;
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%p1 = getelementptr inbounds i16, i16* %p0, i64 1
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%p2 = getelementptr inbounds i16, i16* %p0, i64 2
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@ -1112,18 +1088,27 @@ define i16 @smin_intrinsic_rdx_v8i16(i16* %p0) {
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}
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define i64 @umax_intrinsic_rdx_v4i64(i64* %p0) {
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; CHECK-LABEL: @umax_intrinsic_rdx_v4i64(
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; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i64, i64* [[P0:%.*]], i64 1
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; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i64, i64* [[P0]], i64 2
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; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds i64, i64* [[P0]], i64 3
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; CHECK-NEXT: [[T0:%.*]] = load i64, i64* [[P0]], align 4
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; CHECK-NEXT: [[T1:%.*]] = load i64, i64* [[P1]], align 4
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; CHECK-NEXT: [[T2:%.*]] = load i64, i64* [[P2]], align 4
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; CHECK-NEXT: [[T3:%.*]] = load i64, i64* [[P3]], align 4
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; CHECK-NEXT: [[M10:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T1]], i64 [[T0]])
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; CHECK-NEXT: [[M32:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T3]], i64 [[T2]])
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; CHECK-NEXT: [[M:%.*]] = tail call i64 @llvm.umax.i64(i64 [[M32]], i64 [[M10]])
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; CHECK-NEXT: ret i64 [[M]]
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; DEFAULT-LABEL: @umax_intrinsic_rdx_v4i64(
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; DEFAULT-NEXT: [[P1:%.*]] = getelementptr inbounds i64, i64* [[P0:%.*]], i64 1
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; DEFAULT-NEXT: [[P2:%.*]] = getelementptr inbounds i64, i64* [[P0]], i64 2
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; DEFAULT-NEXT: [[P3:%.*]] = getelementptr inbounds i64, i64* [[P0]], i64 3
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; DEFAULT-NEXT: [[T0:%.*]] = load i64, i64* [[P0]], align 4
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; DEFAULT-NEXT: [[T1:%.*]] = load i64, i64* [[P1]], align 4
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; DEFAULT-NEXT: [[T2:%.*]] = load i64, i64* [[P2]], align 4
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; DEFAULT-NEXT: [[T3:%.*]] = load i64, i64* [[P3]], align 4
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; DEFAULT-NEXT: [[M10:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T1]], i64 [[T0]])
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; DEFAULT-NEXT: [[M32:%.*]] = tail call i64 @llvm.umax.i64(i64 [[T3]], i64 [[T2]])
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; DEFAULT-NEXT: [[M:%.*]] = tail call i64 @llvm.umax.i64(i64 [[M32]], i64 [[M10]])
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; DEFAULT-NEXT: ret i64 [[M]]
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;
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; THRESH-LABEL: @umax_intrinsic_rdx_v4i64(
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; THRESH-NEXT: [[P1:%.*]] = getelementptr inbounds i64, i64* [[P0:%.*]], i64 1
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; THRESH-NEXT: [[P2:%.*]] = getelementptr inbounds i64, i64* [[P0]], i64 2
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; THRESH-NEXT: [[P3:%.*]] = getelementptr inbounds i64, i64* [[P0]], i64 3
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; THRESH-NEXT: [[TMP1:%.*]] = bitcast i64* [[P0]] to <4 x i64>*
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; THRESH-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* [[TMP1]], align 4
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; THRESH-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> [[TMP2]])
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; THRESH-NEXT: ret i64 [[TMP3]]
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;
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%p1 = getelementptr inbounds i64, i64* %p0, i64 1
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%p2 = getelementptr inbounds i64, i64* %p0, i64 2
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@ -1155,38 +1140,10 @@ define i8 @umin_intrinsic_rdx_v16i8(i8* %p0) {
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; CHECK-NEXT: [[PD:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 13
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; CHECK-NEXT: [[PE:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 14
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; CHECK-NEXT: [[PF:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 15
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; CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[P0]], align 4
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; CHECK-NEXT: [[T1:%.*]] = load i8, i8* [[P1]], align 4
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; CHECK-NEXT: [[T2:%.*]] = load i8, i8* [[P2]], align 4
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; CHECK-NEXT: [[T3:%.*]] = load i8, i8* [[P3]], align 4
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; CHECK-NEXT: [[T4:%.*]] = load i8, i8* [[P4]], align 4
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; CHECK-NEXT: [[T5:%.*]] = load i8, i8* [[P5]], align 4
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; CHECK-NEXT: [[T6:%.*]] = load i8, i8* [[P6]], align 4
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; CHECK-NEXT: [[T7:%.*]] = load i8, i8* [[P7]], align 4
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; CHECK-NEXT: [[T8:%.*]] = load i8, i8* [[P8]], align 4
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; CHECK-NEXT: [[T9:%.*]] = load i8, i8* [[P9]], align 4
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; CHECK-NEXT: [[TA:%.*]] = load i8, i8* [[PA]], align 4
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; CHECK-NEXT: [[TB:%.*]] = load i8, i8* [[PB]], align 4
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; CHECK-NEXT: [[TC:%.*]] = load i8, i8* [[PC]], align 4
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; CHECK-NEXT: [[TD:%.*]] = load i8, i8* [[PD]], align 4
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; CHECK-NEXT: [[TE:%.*]] = load i8, i8* [[PE]], align 4
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; CHECK-NEXT: [[TF:%.*]] = load i8, i8* [[PF]], align 4
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; CHECK-NEXT: [[M10:%.*]] = tail call i8 @llvm.umin.i8(i8 [[T1]], i8 [[T0]])
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; CHECK-NEXT: [[M32:%.*]] = tail call i8 @llvm.umin.i8(i8 [[T3]], i8 [[T2]])
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; CHECK-NEXT: [[M54:%.*]] = tail call i8 @llvm.umin.i8(i8 [[T5]], i8 [[T4]])
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; CHECK-NEXT: [[M76:%.*]] = tail call i8 @llvm.umin.i8(i8 [[T7]], i8 [[T6]])
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; CHECK-NEXT: [[M98:%.*]] = tail call i8 @llvm.umin.i8(i8 [[T9]], i8 [[T8]])
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; CHECK-NEXT: [[MBA:%.*]] = tail call i8 @llvm.umin.i8(i8 [[TB]], i8 [[TA]])
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; CHECK-NEXT: [[MDC:%.*]] = tail call i8 @llvm.umin.i8(i8 [[TD]], i8 [[TC]])
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; CHECK-NEXT: [[MFE:%.*]] = tail call i8 @llvm.umin.i8(i8 [[TF]], i8 [[TE]])
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; CHECK-NEXT: [[M3210:%.*]] = tail call i8 @llvm.umin.i8(i8 [[M32]], i8 [[M10]])
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; CHECK-NEXT: [[M7654:%.*]] = tail call i8 @llvm.umin.i8(i8 [[M76]], i8 [[M54]])
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; CHECK-NEXT: [[MDC98:%.*]] = tail call i8 @llvm.umin.i8(i8 [[MDC]], i8 [[M98]])
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; CHECK-NEXT: [[MFEBA:%.*]] = tail call i8 @llvm.umin.i8(i8 [[MFE]], i8 [[MBA]])
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; CHECK-NEXT: [[ML:%.*]] = tail call i8 @llvm.umin.i8(i8 [[M3210]], i8 [[M7654]])
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; CHECK-NEXT: [[MH:%.*]] = tail call i8 @llvm.umin.i8(i8 [[MFEBA]], i8 [[MDC98]])
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; CHECK-NEXT: [[M:%.*]] = tail call i8 @llvm.umin.i8(i8 [[MH]], i8 [[ML]])
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; CHECK-NEXT: ret i8 [[M]]
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[P0]] to <16 x i8>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> [[TMP2]])
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; CHECK-NEXT: ret i8 [[TMP3]]
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;
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%p1 = getelementptr inbounds i8, i8* %p0, i64 1
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%p2 = getelementptr inbounds i8, i8* %p0, i64 2
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@ -1241,21 +1198,13 @@ define i8 @umin_intrinsic_rdx_v16i8(i8* %p0) {
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define void @PR49730() {
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; CHECK-LABEL: @PR49730(
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; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.smin.i32(i32 undef, i32 2)
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; CHECK-NEXT: [[T1:%.*]] = sub nsw i32 undef, [[T]]
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; CHECK-NEXT: [[T2:%.*]] = call i32 @llvm.umin.i32(i32 undef, i32 [[T1]])
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; CHECK-NEXT: [[T3:%.*]] = call i32 @llvm.smin.i32(i32 undef, i32 2)
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; CHECK-NEXT: [[T4:%.*]] = sub nsw i32 undef, [[T3]]
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; CHECK-NEXT: [[T5:%.*]] = call i32 @llvm.umin.i32(i32 [[T2]], i32 [[T4]])
|
||||
; CHECK-NEXT: [[T6:%.*]] = call i32 @llvm.smin.i32(i32 undef, i32 1)
|
||||
; CHECK-NEXT: [[T7:%.*]] = sub nuw nsw i32 undef, [[T6]]
|
||||
; CHECK-NEXT: [[T8:%.*]] = call i32 @llvm.umin.i32(i32 [[T5]], i32 [[T7]])
|
||||
; CHECK-NEXT: [[T9:%.*]] = call i32 @llvm.smin.i32(i32 undef, i32 1)
|
||||
; CHECK-NEXT: [[T10:%.*]] = sub nsw i32 undef, [[T9]]
|
||||
; CHECK-NEXT: [[T11:%.*]] = call i32 @llvm.umin.i32(i32 [[T8]], i32 [[T10]])
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 1, i32 1>)
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = sub nsw <4 x i32> undef, [[TMP1]]
|
||||
; CHECK-NEXT: [[T12:%.*]] = sub nsw i32 undef, undef
|
||||
; CHECK-NEXT: [[T13:%.*]] = call i32 @llvm.umin.i32(i32 [[T11]], i32 [[T12]])
|
||||
; CHECK-NEXT: [[T14:%.*]] = call i32 @llvm.umin.i32(i32 [[T13]], i32 93)
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP2]])
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP3]], i32 [[T12]])
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP4]], i32 undef)
|
||||
; CHECK-NEXT: [[T14:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP5]], i32 93)
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
%t = call i32 @llvm.smin.i32(i32 undef, i32 2)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
||||
; RUN: opt < %s -mtriple=x86_64-unknown-linux -slp-vectorizer -S | FileCheck %s
|
||||
; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx -slp-vectorizer -S | FileCheck %s
|
||||
; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=core-avx2 -slp-vectorizer -S | FileCheck %s
|
||||
; RUN: opt < %s -mtriple=x86_64-unknown-linux -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
|
||||
; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
|
||||
; RUN: opt < %s -mtriple=x86_64-unknown-linux -mcpu=core-avx2 -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
|
||||
|
||||
@arr = local_unnamed_addr global [32 x i32] zeroinitializer, align 16
|
||||
|
||||
|
|
@ -21,15 +21,20 @@ define i32 @smax_v2i32(i32) {
|
|||
}
|
||||
|
||||
define i32 @smax_v4i32(i32) {
|
||||
; CHECK-LABEL: @smax_v4i32(
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 0), align 16
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 1), align 4
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 2), align 8
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 3), align 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP2]], i32 [[TMP3]])
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP6]], i32 [[TMP4]])
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP7]], i32 [[TMP5]])
|
||||
; CHECK-NEXT: ret i32 [[TMP8]]
|
||||
; SSE-LABEL: @smax_v4i32(
|
||||
; SSE-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 0), align 16
|
||||
; SSE-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 1), align 4
|
||||
; SSE-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 2), align 8
|
||||
; SSE-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 3), align 4
|
||||
; SSE-NEXT: [[TMP6:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP2]], i32 [[TMP3]])
|
||||
; SSE-NEXT: [[TMP7:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP6]], i32 [[TMP4]])
|
||||
; SSE-NEXT: [[TMP8:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP7]], i32 [[TMP5]])
|
||||
; SSE-NEXT: ret i32 [[TMP8]]
|
||||
;
|
||||
; AVX-LABEL: @smax_v4i32(
|
||||
; AVX-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([32 x i32]* @arr to <4 x i32>*), align 16
|
||||
; AVX-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP2]])
|
||||
; AVX-NEXT: ret i32 [[TMP3]]
|
||||
;
|
||||
%2 = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 0), align 16
|
||||
%3 = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 1), align 4
|
||||
|
|
@ -43,22 +48,9 @@ define i32 @smax_v4i32(i32) {
|
|||
|
||||
define i32 @smax_v8i32(i32) {
|
||||
; CHECK-LABEL: @smax_v8i32(
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 0), align 16
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 1), align 4
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 2), align 8
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 3), align 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 4), align 16
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 5), align 4
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 6), align 8
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 7), align 4
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP2]], i32 [[TMP3]])
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP10]], i32 [[TMP4]])
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP11]], i32 [[TMP5]])
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP12]], i32 [[TMP6]])
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP13]], i32 [[TMP7]])
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP14]], i32 [[TMP8]])
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP15]], i32 [[TMP9]])
|
||||
; CHECK-NEXT: ret i32 [[TMP16]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([32 x i32]* @arr to <8 x i32>*), align 16
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> [[TMP2]])
|
||||
; CHECK-NEXT: ret i32 [[TMP3]]
|
||||
;
|
||||
%2 = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 0), align 16
|
||||
%3 = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 1), align 4
|
||||
|
|
@ -80,38 +72,9 @@ define i32 @smax_v8i32(i32) {
|
|||
|
||||
define i32 @smax_v16i32(i32) {
|
||||
; CHECK-LABEL: @smax_v16i32(
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 0), align 16
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 1), align 4
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 2), align 8
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 3), align 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 4), align 16
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 5), align 4
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 6), align 8
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 7), align 4
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 8), align 16
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 9), align 4
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 10), align 8
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 11), align 4
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 12), align 16
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 13), align 4
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 14), align 8
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 15), align 4
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP2]], i32 [[TMP3]])
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP18]], i32 [[TMP4]])
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP19]], i32 [[TMP5]])
|
||||
; CHECK-NEXT: [[TMP21:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP20]], i32 [[TMP6]])
|
||||
; CHECK-NEXT: [[TMP22:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP21]], i32 [[TMP7]])
|
||||
; CHECK-NEXT: [[TMP23:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP22]], i32 [[TMP8]])
|
||||
; CHECK-NEXT: [[TMP24:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP23]], i32 [[TMP9]])
|
||||
; CHECK-NEXT: [[TMP25:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP24]], i32 [[TMP10]])
|
||||
; CHECK-NEXT: [[TMP26:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP25]], i32 [[TMP11]])
|
||||
; CHECK-NEXT: [[TMP27:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP26]], i32 [[TMP12]])
|
||||
; CHECK-NEXT: [[TMP28:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP27]], i32 [[TMP13]])
|
||||
; CHECK-NEXT: [[TMP29:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP28]], i32 [[TMP14]])
|
||||
; CHECK-NEXT: [[TMP30:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP29]], i32 [[TMP15]])
|
||||
; CHECK-NEXT: [[TMP31:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP30]], i32 [[TMP16]])
|
||||
; CHECK-NEXT: [[TMP32:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP31]], i32 [[TMP17]])
|
||||
; CHECK-NEXT: ret i32 [[TMP32]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i32>, <16 x i32>* bitcast ([32 x i32]* @arr to <16 x i32>*), align 16
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> [[TMP2]])
|
||||
; CHECK-NEXT: ret i32 [[TMP3]]
|
||||
;
|
||||
%2 = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 0), align 16
|
||||
%3 = load i32, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @arr, i64 0, i64 1), align 4
|
||||
|
|
|
|||
|
|
@ -43,19 +43,11 @@ declare i32 @llvm.umin.i32(i32, i32)
|
|||
define void @test2() {
|
||||
; CHECK-LABEL: @test2(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[SMIN0:%.*]] = call i32 @llvm.smin.i32(i32 undef, i32 0)
|
||||
; CHECK-NEXT: [[SMIN1:%.*]] = call i32 @llvm.smin.i32(i32 undef, i32 1)
|
||||
; CHECK-NEXT: [[SMIN2:%.*]] = call i32 @llvm.smin.i32(i32 undef, i32 2)
|
||||
; CHECK-NEXT: [[SMIN3:%.*]] = call i32 @llvm.smin.i32(i32 undef, i32 3)
|
||||
; CHECK-NEXT: [[A:%.*]] = sub nsw i32 undef, [[SMIN0]]
|
||||
; CHECK-NEXT: [[B:%.*]] = sub nsw i32 undef, [[SMIN1]]
|
||||
; CHECK-NEXT: [[C:%.*]] = sub nsw i32 undef, [[SMIN2]]
|
||||
; CHECK-NEXT: [[D:%.*]] = sub nsw i32 undef, [[SMIN3]]
|
||||
; CHECK-NEXT: [[UMIN0:%.*]] = call i32 @llvm.umin.i32(i32 [[D]], i32 [[C]])
|
||||
; CHECK-NEXT: [[UMIN1:%.*]] = call i32 @llvm.umin.i32(i32 [[UMIN0]], i32 [[B]])
|
||||
; CHECK-NEXT: [[UMIN2:%.*]] = call i32 @llvm.umin.i32(i32 [[UMIN1]], i32 [[A]])
|
||||
; CHECK-NEXT: [[UMIN3:%.*]] = call i32 @llvm.umin.i32(i32 [[UMIN2]], i32 77)
|
||||
; CHECK-NEXT: [[E:%.*]] = icmp ugt i32 [[UMIN3]], 1
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = sub nsw <4 x i32> undef, [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> [[TMP1]])
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.umin.i32(i32 [[TMP2]], i32 77)
|
||||
; CHECK-NEXT: [[E:%.*]] = icmp ugt i32 [[TMP3]], 1
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
|
|
|
|||
Loading…
Reference in New Issue