forked from OSchip/llvm-project
[ARM][LowOverheadLoops] Merge VCMP and VPST across VPT blocks
This patch adds support for combining a VPST with a dangling VCMP from a previous VPT block. Differential Revision: https://reviews.llvm.org/D90935
This commit is contained in:
Sam Tebbs
parent
871fe71f29
commit
da2e4728c7
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@ -87,8 +87,8 @@ static bool isVectorPredicate(MachineInstr *MI) {
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return MI->findRegisterDefOperandIdx(ARM::VPR) != -1;
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}
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static bool hasVPRUse(MachineInstr *MI) {
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return MI->findRegisterUseOperandIdx(ARM::VPR) != -1;
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static bool hasVPRUse(MachineInstr &MI) {
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return MI.findRegisterUseOperandIdx(ARM::VPR) != -1;
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}
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static bool isDomainMVE(MachineInstr *MI) {
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@ -97,8 +97,7 @@ static bool isDomainMVE(MachineInstr *MI) {
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}
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static bool shouldInspect(MachineInstr &MI) {
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return isDomainMVE(&MI) || isVectorPredicate(&MI) ||
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hasVPRUse(&MI);
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return isDomainMVE(&MI) || isVectorPredicate(&MI) || hasVPRUse(MI);
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}
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static bool isDo(MachineInstr *MI) {
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@ -1485,14 +1484,33 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
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for (auto &Block : LoLoop.getVPTBlocks()) {
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SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
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auto ReplaceVCMPWithVPT = [&](MachineInstr *&TheVCMP, MachineInstr *At) {
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assert(TheVCMP && "Replacing a removed or non-existent VCMP");
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// Replace the VCMP with a VPT
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MachineInstrBuilder MIB =
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BuildMI(*At->getParent(), At, At->getDebugLoc(),
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TII->get(VCMPOpcodeToVPT(TheVCMP->getOpcode())));
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MIB.addImm(ARMVCC::Then);
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// Register one
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MIB.add(TheVCMP->getOperand(1));
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// Register two
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MIB.add(TheVCMP->getOperand(2));
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// The comparison code, e.g. ge, eq, lt
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MIB.add(TheVCMP->getOperand(3));
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LLVM_DEBUG(dbgs() << "ARM Loops: Combining with VCMP to VPT: " << *MIB);
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LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
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LoLoop.ToRemove.insert(TheVCMP);
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TheVCMP = nullptr;
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};
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if (VPTState::isEntryPredicatedOnVCTP(Block, /*exclusive*/ true)) {
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MachineInstr *VPST = Insts.front();
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if (VPTState::hasUniformPredicate(Block)) {
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// A vpt block starting with VPST, is only predicated upon vctp and has no
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// internal vpr defs:
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// - Remove vpst.
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// - Unpredicate the remaining instructions.
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LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *Insts.front());
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LoLoop.ToRemove.insert(Insts.front());
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LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
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for (unsigned i = 1; i < Insts.size(); ++i)
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RemovePredicate(Insts[i]);
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} else {
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@ -1503,10 +1521,7 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
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// we come across the divergent vpr def.
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// - Insert a new vpst to predicate the instruction(s) that following
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// the divergent vpr def.
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// TODO: We could be producing more VPT blocks than necessary and could
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// fold the newly created one into a proceeding one.
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MachineInstr *Divergent = VPTState::getDivergent(Block);
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MachineInstr *VPST = Insts.front();
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auto DivergentNext = ++MachineBasicBlock::iterator(Divergent);
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bool DivergentNextIsPredicated =
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getVPTInstrPredicate(*DivergentNext) != ARMVCC::None;
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@ -1520,24 +1535,6 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
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MachineInstr *VCMP =
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VCMPOpcodeToVPT(Divergent->getOpcode()) != 0 ? Divergent : nullptr;
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auto ReplaceVCMPWithVPT = [&]() {
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// Replace the VCMP with a VPT
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MachineInstrBuilder MIB = BuildMI(
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*Divergent->getParent(), Divergent, Divergent->getDebugLoc(),
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TII->get(VCMPOpcodeToVPT(VCMP->getOpcode())));
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MIB.addImm(ARMVCC::Then);
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// Register one
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MIB.add(VCMP->getOperand(1));
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// Register two
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MIB.add(VCMP->getOperand(2));
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// The comparison code, e.g. ge, eq, lt
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MIB.add(VCMP->getOperand(3));
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LLVM_DEBUG(dbgs()
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<< "ARM Loops: Combining with VCMP to VPT: " << *MIB);
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LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
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LoLoop.ToRemove.insert(VCMP);
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};
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if (DivergentNextIsPredicated) {
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// Insert a VPST at the divergent only if the next instruction
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// would actually use it. A VCMP following a VPST can be
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@ -1553,17 +1550,48 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
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LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
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} else {
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// No RDA checks are necessary here since the VPST would have been
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// directly before the VCMP
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ReplaceVCMPWithVPT();
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// directly after the VCMP
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ReplaceVCMPWithVPT(VCMP, VCMP);
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}
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}
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}
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LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
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LoLoop.ToRemove.insert(VPST);
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}
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} else if (Block.containsVCTP()) {
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// The vctp will be removed, so the block mask of the vp(s)t will need
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// to be recomputed.
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LoLoop.BlockMasksToRecompute.insert(Insts.front());
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} else if (Insts.front()->getOpcode() == ARM::MVE_VPST) {
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// If this block starts with a VPST then attempt to merge it with the
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// preceeding un-merged VCMP into a VPT. This VCMP comes from a VPT
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// block that no longer exists
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MachineInstr *VPST = Insts.front();
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auto Next = ++MachineBasicBlock::iterator(VPST);
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assert(getVPTInstrPredicate(*Next) != ARMVCC::None &&
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"The instruction after a VPST must be predicated");
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MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR);
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if (VprDef && VCMPOpcodeToVPT(VprDef->getOpcode()) &&
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!LoLoop.ToRemove.contains(VprDef)) {
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MachineInstr *VCMP = VprDef;
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// The VCMP and VPST can only be merged if the VCMP's operands will have
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// the same values at the VPST
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if (RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) &&
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RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(2).getReg())) {
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bool IntermediateInstrsUseVPR =
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std::any_of(++MachineBasicBlock::iterator(VCMP),
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MachineBasicBlock::iterator(VPST), hasVPRUse);
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// If the instruction after the VCMP is predicated then a different
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// code path is expected to have merged the VCMP and VPST already.
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// This assertion protects against changes to that behaviour
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assert(!IntermediateInstrsUseVPR &&
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"Instructions between the VCMP and VPST are not expected to "
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"be predicated");
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ReplaceVCMPWithVPT(VCMP, VPST);
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LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
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LoLoop.ToRemove.insert(VPST);
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}
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}
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}
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}
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@ -0,0 +1,479 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
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--- |
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define void @combine_previous() {
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while.end6:
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ret void
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}
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define void @combine_middle() {
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while.end6:
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ret void
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}
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define void @combine_last() {
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while.end6:
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ret void
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}
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define void @no_combination_diff_reg_value() {
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while.end6:
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ret void
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}
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define void @no_combination_vcmp_already_merged() {
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while.end6:
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ret void
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}
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...
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---
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name: combine_previous
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alignment: 8
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants:
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- id: 0
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value: float 0xC7EFFFFFE0000000
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alignment: 4
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isTargetSpecific: false
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: combine_previous
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $r0, $r1
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; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
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; CHECK: bb.1 (align 4):
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; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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; CHECK: liveins: $lr, $q0, $r0
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; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
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; CHECK: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0
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; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
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; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q0
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
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; CHECK: bb.2:
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; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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; CHECK: bb.3 (align 4):
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; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
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bb.0:
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successors: %bb.6(0x80000000)
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liveins: $r0, $r1, $r2
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renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
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renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
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renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
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renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
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renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
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$lr = t2DoLoopStart renamable $lr
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bb.6 (align 4):
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successors: %bb.6(0x7c000000), %bb.8(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r2
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renamable $lr = t2LoopDec killed renamable $lr, 1
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renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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MVE_VPST 8, implicit $vpr
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renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
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MVE_VPST 4, implicit $vpr
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renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, renamable $q0
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renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
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MVE_VPST 8, implicit $vpr
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renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q0
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t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
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tB %bb.8, 14 /* CC::al */, $noreg
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bb.8:
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liveins: $r2, $r12, $q0
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frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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bb.9 (align 4):
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CONSTPOOL_ENTRY 0, %const.0, 4
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...
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---
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name: combine_middle
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alignment: 8
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants:
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- id: 0
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value: float 0xC7EFFFFFE0000000
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alignment: 4
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isTargetSpecific: false
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: combine_middle
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x80000000)
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; CHECK: liveins: $q2, $r0, $r1
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; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
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; CHECK: bb.1 (align 4):
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; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
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; CHECK: liveins: $lr, $q0, $q2, $r0
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; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
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; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q2
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; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
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; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
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; CHECK: MVE_VPST 4, implicit $vpr
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; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
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; CHECK: bb.2:
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; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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; CHECK: bb.3 (align 4):
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; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
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bb.0:
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successors: %bb.6(0x80000000)
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liveins: $r0, $r1, $r2
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renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
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renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
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renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
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renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
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renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
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$lr = t2DoLoopStart renamable $lr
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bb.6 (align 4):
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successors: %bb.6(0x7c000000), %bb.8(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r2, $q2
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renamable $lr = t2LoopDec killed renamable $lr, 1
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renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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MVE_VPST 2, implicit $vpr
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renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
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renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
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renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
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MVE_VPST 8, implicit $vpr
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renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
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MVE_VPST 4, implicit $vpr
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renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
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t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
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tB %bb.8, 14 /* CC::al */, $noreg
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bb.8:
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liveins: $r2, $r12, $q0
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frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
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|
||||
bb.9 (align 4):
|
||||
CONSTPOOL_ENTRY 0, %const.0, 4
|
||||
|
||||
...
|
||||
---
|
||||
name: combine_last
|
||||
alignment: 8
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
hasWinCFI: false
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
- { reg: '$r1', virtual-reg: '' }
|
||||
- { reg: '$r2', virtual-reg: '' }
|
||||
frameInfo:
|
||||
fixedStack: []
|
||||
stack:
|
||||
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
callSites: []
|
||||
debugValueSubstitutions: []
|
||||
constants:
|
||||
- id: 0
|
||||
value: float 0xC7EFFFFFE0000000
|
||||
alignment: 4
|
||||
isTargetSpecific: false
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: combine_last
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $q2, $r0, $r1
|
||||
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
|
||||
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
|
||||
; CHECK: bb.1 (align 4):
|
||||
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
; CHECK: liveins: $lr, $q0, $q2, $r0
|
||||
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
|
||||
; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
|
||||
; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q2
|
||||
; CHECK: MVE_VPTv4f32 8, renamable $q2, renamable $q1, 12, implicit-def $vpr
|
||||
; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1
|
||||
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
|
||||
; CHECK: bb.2:
|
||||
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
; CHECK: bb.3 (align 4):
|
||||
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
|
||||
bb.0:
|
||||
successors: %bb.6(0x80000000)
|
||||
liveins: $r0, $r1, $r2
|
||||
|
||||
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
|
||||
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
|
||||
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
|
||||
$lr = t2DoLoopStart renamable $lr
|
||||
|
||||
bb.6 (align 4):
|
||||
successors: %bb.6(0x7c000000), %bb.8(0x04000000)
|
||||
liveins: $lr, $q0, $r0, $r1, $r2, $q2
|
||||
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
|
||||
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
|
||||
MVE_VPST 2, implicit $vpr
|
||||
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
|
||||
renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
|
||||
renamable $vpr = MVE_VCMPf32 renamable $q2, renamable $q1, 12, 1, killed renamable $vpr
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
|
||||
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
|
||||
tB %bb.8, 14 /* CC::al */, $noreg
|
||||
|
||||
bb.8:
|
||||
liveins: $r2, $r12, $q0
|
||||
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
|
||||
bb.9 (align 4):
|
||||
CONSTPOOL_ENTRY 0, %const.0, 4
|
||||
|
||||
...
|
||||
---
|
||||
name: no_combination_diff_reg_value
|
||||
alignment: 8
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
hasWinCFI: false
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
- { reg: '$r1', virtual-reg: '' }
|
||||
- { reg: '$r2', virtual-reg: '' }
|
||||
frameInfo:
|
||||
fixedStack: []
|
||||
stack:
|
||||
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
callSites: []
|
||||
debugValueSubstitutions: []
|
||||
constants:
|
||||
- id: 0
|
||||
value: float 0xC7EFFFFFE0000000
|
||||
alignment: 4
|
||||
isTargetSpecific: false
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: no_combination_diff_reg_value
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $r0, $r1
|
||||
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
|
||||
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
|
||||
; CHECK: bb.1 (align 4):
|
||||
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
; CHECK: liveins: $lr, $q0, $r0
|
||||
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
|
||||
; CHECK: renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 0, $noreg, killed renamable $q1
|
||||
; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 0, killed $noreg
|
||||
; CHECK: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0
|
||||
; CHECK: MVE_VPST 8, implicit $vpr
|
||||
; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q0
|
||||
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
|
||||
; CHECK: bb.2:
|
||||
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
; CHECK: bb.3 (align 4):
|
||||
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
|
||||
bb.0:
|
||||
successors: %bb.6(0x80000000)
|
||||
liveins: $r0, $r1, $r2
|
||||
|
||||
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
|
||||
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
|
||||
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
|
||||
$lr = t2DoLoopStart renamable $lr
|
||||
|
||||
bb.6 (align 4):
|
||||
successors: %bb.6(0x7c000000), %bb.8(0x04000000)
|
||||
liveins: $lr, $q0, $r0, $r1, $r2
|
||||
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
|
||||
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
|
||||
MVE_VPST 4, implicit $vpr
|
||||
renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
|
||||
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
|
||||
renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q0
|
||||
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
|
||||
tB %bb.8, 14 /* CC::al */, $noreg
|
||||
|
||||
bb.8:
|
||||
liveins: $r2, $r12, $q0
|
||||
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
|
||||
bb.9 (align 4):
|
||||
CONSTPOOL_ENTRY 0, %const.0, 4
|
||||
|
||||
...
|
||||
---
|
||||
name: no_combination_vcmp_already_merged
|
||||
alignment: 8
|
||||
exposesReturnsTwice: false
|
||||
legalized: false
|
||||
regBankSelected: false
|
||||
selected: false
|
||||
failedISel: false
|
||||
tracksRegLiveness: true
|
||||
hasWinCFI: false
|
||||
registers: []
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '' }
|
||||
- { reg: '$r1', virtual-reg: '' }
|
||||
- { reg: '$r2', virtual-reg: '' }
|
||||
frameInfo:
|
||||
fixedStack: []
|
||||
stack:
|
||||
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
||||
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
||||
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
callSites: []
|
||||
debugValueSubstitutions: []
|
||||
constants:
|
||||
- id: 0
|
||||
value: float 0xC7EFFFFFE0000000
|
||||
alignment: 4
|
||||
isTargetSpecific: false
|
||||
machineFunctionInfo: {}
|
||||
body: |
|
||||
; CHECK-LABEL: name: no_combination_vcmp_already_merged
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $q2, $r0, $r1
|
||||
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
|
||||
; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
|
||||
; CHECK: bb.1 (align 4):
|
||||
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
||||
; CHECK: liveins: $lr, $q0, $q2, $r0
|
||||
; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
|
||||
; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
|
||||
; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
|
||||
; CHECK: MVE_VPST 8, implicit $vpr
|
||||
; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1
|
||||
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
|
||||
; CHECK: bb.2:
|
||||
; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
; CHECK: bb.3 (align 4):
|
||||
; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
|
||||
bb.0:
|
||||
successors: %bb.6(0x80000000)
|
||||
liveins: $r0, $r1, $r2
|
||||
|
||||
renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
|
||||
renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
|
||||
renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
|
||||
renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
|
||||
$lr = t2DoLoopStart renamable $lr
|
||||
|
||||
bb.6 (align 4):
|
||||
successors: %bb.6(0x7c000000), %bb.8(0x04000000)
|
||||
liveins: $lr, $q0, $r0, $r1, $r2, $q2
|
||||
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
|
||||
renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
|
||||
MVE_VPST 4, implicit $vpr
|
||||
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
|
||||
renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
|
||||
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
|
||||
tB %bb.8, 14 /* CC::al */, $noreg
|
||||
|
||||
bb.8:
|
||||
liveins: $r2, $r12, $q0
|
||||
frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
|
||||
|
||||
bb.9 (align 4):
|
||||
CONSTPOOL_ENTRY 0, %const.0, 4
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue