forked from OSchip/llvm-project
[AVX-512] Use sse_load_f32/f64 in place of scalar_to_vector and scalar load in some patterns.
llvm-svn: 295693
This commit is contained in:
Craig Topper
parent
63b7d71844
commit
d9fe664868
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@ -92,6 +92,12 @@ class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
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PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
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ComplexPattern ScalarIntMemCPat = !if (!eq (EltTypeName, "f32"),
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!cast<ComplexPattern>("sse_load_f32"),
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!if (!eq (EltTypeName, "f64"),
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!cast<ComplexPattern>("sse_load_f64"),
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?));
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// The corresponding float type, e.g. v16f32 for v16i32
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// Note: For EltSize < 32, FloatVT is illegal and TableGen
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// fails to compile, so we choose FloatVT = VT
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@ -1518,11 +1524,10 @@ multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>
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imm:$cc)>, EVEX_4V;
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defm rm_Int : AVX512_maskable_cmp<0xC2, MRMSrcMem, _,
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(outs _.KRC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2, AVXCC:$cc),
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(ins _.RC:$src1, _.IntScalarMemOp:$src2, AVXCC:$cc),
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"vcmp${cc}"#_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(OpNode (_.VT _.RC:$src1),
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(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
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(OpNode (_.VT _.RC:$src1), _.ScalarIntMemCPat:$src2,
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imm:$cc)>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VT1>;
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defm rrb_Int : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
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@ -4140,16 +4145,16 @@ multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
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defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
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(i32 FROUND_CURRENT)),
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(_.VT (VecNode _.RC:$src1, _.RC:$src2,
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(i32 FROUND_CURRENT))),
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itins.rr>;
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defm rm_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr,
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(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr,
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"$src2, $src1", "$src1, $src2",
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(VecNode (_.VT _.RC:$src1),
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(_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
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(i32 FROUND_CURRENT)),
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(_.VT (VecNode _.RC:$src1,
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_.ScalarIntMemCPat:$src2,
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(i32 FROUND_CURRENT))),
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itins.rm>;
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let isCodeGenOnly = 1, Predicates = [HasAVX512] in {
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def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
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@ -5512,7 +5517,7 @@ multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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"$src3, $src2", "$src2, $src3", RHS_VEC_r, 1, 1>, AVX512FMA3Base;
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defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.ScalarMemOp:$src3), OpcodeStr,
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(ins _.RC:$src2, _.IntScalarMemOp:$src3), OpcodeStr,
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"$src3, $src2", "$src2, $src3", RHS_VEC_m, 1, 1>, AVX512FMA3Base;
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defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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@ -5544,7 +5549,7 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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// semantics.
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3, (i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2,
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(_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))), (i32 FROUND_CURRENT))),
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_.ScalarIntMemCPat:$src3, (i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3,
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(i32 imm:$rc))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
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@ -5554,8 +5559,7 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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defm NAME#231#SUFF#Z: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix , _ ,
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(_.VT (OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds3 _.RC:$src2,
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(_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
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(_.VT (OpNodeRnds3 _.RC:$src2, _.ScalarIntMemCPat:$src3,
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_.RC:$src1, (i32 FROUND_CURRENT))),
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(_.VT ( OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1,
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(i32 imm:$rc))),
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@ -5566,8 +5570,7 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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defm NAME#132#SUFF#Z: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix , _ ,
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1,
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(_.VT (scalar_to_vector(_.ScalarLdFrag addr:$src3))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.ScalarIntMemCPat:$src3,
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_.RC:$src2, (i32 FROUND_CURRENT))),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src3, _.RC:$src2,
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(i32 imm:$rc))),
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@ -4,10 +4,9 @@
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define i8 @test_int_x86_avx512_mask_cmp_ss(<4 x float> %a, float* %b, i8 %mask) {
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; CHECK-LABEL: test_int_x86_avx512_mask_cmp_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vcmpunordss %xmm1, %xmm0, %k0 {%k1}
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; CHECK-NEXT: vcmpunordss (%rdi), %xmm0, %k0 {%k1}
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; CHECK-NEXT: kmovw %k0, %eax
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; CHECK-NEXT: andl $1, %eax
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; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
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@ -25,10 +24,9 @@ declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)
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define <4 x float> @test_mask_max_ss(<4 x float> %a, float* %b, i8 %mask) {
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; CHECK-LABEL: test_mask_max_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vmaxss %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: vmaxss (%rdi), %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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%b.val = load float, float* %b
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%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
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@ -43,10 +41,9 @@ declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>,
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define <4 x float> @test_maskz_add_ss(<4 x float> %a, float* %b, i8 %mask) {
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; CHECK-LABEL: test_maskz_add_ss:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vaddss %xmm1, %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: vaddss (%rdi), %xmm0, %xmm0 {%k1} {z}
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; CHECK-NEXT: retq
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%b.val = load float, float* %b
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%bv0 = insertelement <4 x float> undef, float %b.val, i32 0
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@ -64,10 +61,9 @@ declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double>, <2 x double>,
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define <2 x double> @test_int_x86_avx512_mask_vfmadd_sd(<2 x double> %a, <2 x double> %b, double* %c, i8 %mask){
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; CHECK-LABEL: test_int_x86_avx512_mask_vfmadd_sd:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
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; CHECK-NEXT: andl $1, %esi
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; CHECK-NEXT: kmovw %esi, %k1
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; CHECK-NEXT: vfmadd213sd %xmm2, %xmm1, %xmm0 {%k1}
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; CHECK-NEXT: vfmadd213sd (%rdi), %xmm1, %xmm0 {%k1}
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; CHECK-NEXT: retq
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%c.val = load double, double* %c
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%cv0 = insertelement <2 x double> undef, double %c.val, i32 0
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