forked from OSchip/llvm-project
[Refactor] Use non-const MemoryAccess base addresses
llvm-svn: 214168
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@ -103,7 +103,9 @@ private:
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isl_map *AccessRelation;
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isl_map *AccessRelation;
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enum AccessType Type;
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enum AccessType Type;
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const Value *BaseAddr;
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/// @brief The base address (e.g., A for A[i+j]).
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Value *BaseAddr;
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std::string BaseName;
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std::string BaseName;
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isl_basic_map *createBasicAccessMap(ScopStmt *Statement);
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isl_basic_map *createBasicAccessMap(ScopStmt *Statement);
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ScopStmt *Statement;
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ScopStmt *Statement;
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@ -178,7 +180,8 @@ public:
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/// @brief Get an isl string representing this access function.
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/// @brief Get an isl string representing this access function.
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std::string getAccessRelationStr() const;
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std::string getAccessRelationStr() const;
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const Value *getBaseAddr() const { return BaseAddr; }
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/// @brief Get the base address of this access (e.g. A for A[i+j]).
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Value *getBaseAddr() const { return BaseAddr; }
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const std::string &getBaseName() const { return BaseName; }
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const std::string &getBaseName() const { return BaseName; }
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@ -35,7 +35,7 @@ extern bool PollyDelinearize;
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/// @brief A memory access described by a SCEV expression and the access type.
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/// @brief A memory access described by a SCEV expression and the access type.
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class IRAccess {
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class IRAccess {
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public:
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public:
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const Value *BaseAddress;
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Value *BaseAddress;
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const SCEV *Offset;
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const SCEV *Offset;
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@ -53,7 +53,7 @@ private:
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public:
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public:
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SmallVector<const SCEV *, 4> Subscripts, Sizes;
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SmallVector<const SCEV *, 4> Subscripts, Sizes;
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explicit IRAccess(TypeKind Type, const Value *BaseAddress, const SCEV *Offset,
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explicit IRAccess(TypeKind Type, Value *BaseAddress, const SCEV *Offset,
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unsigned elemBytes, bool Affine,
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unsigned elemBytes, bool Affine,
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SmallVector<const SCEV *, 4> Subscripts,
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SmallVector<const SCEV *, 4> Subscripts,
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SmallVector<const SCEV *, 4> Sizes)
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SmallVector<const SCEV *, 4> Sizes)
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@ -62,7 +62,7 @@ public:
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enum TypeKind getType() const { return Type; }
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enum TypeKind getType() const { return Type; }
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const Value *getBase() const { return BaseAddress; }
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Value *getBase() const { return BaseAddress; }
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const SCEV *getOffset() const { return Offset; }
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const SCEV *getOffset() const { return Offset; }
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@ -307,7 +307,7 @@ Value *BlockGenerator::generateLocationAccessed(const Instruction *Inst,
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NewPointer =
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NewPointer =
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getNewValue(Pointer, BBMap, GlobalMap, LTS, getLoopForInst(Inst));
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getNewValue(Pointer, BBMap, GlobalMap, LTS, getLoopForInst(Inst));
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} else {
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} else {
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Value *BaseAddress = const_cast<Value *>(Access.getBaseAddr());
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Value *BaseAddress = Access.getBaseAddr();
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NewPointer = getNewAccessOperand(NewAccessRelation, BaseAddress, BBMap,
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NewPointer = getNewAccessOperand(NewAccessRelation, BaseAddress, BBMap,
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GlobalMap, LTS, getLoopForInst(Inst));
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GlobalMap, LTS, getLoopForInst(Inst));
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}
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}
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@ -667,7 +667,7 @@ SetVector<Value *> ClastStmtCodeGen::getGPUValues(unsigned &OutputBytes) {
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// Record the memory reference base addresses.
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// Record the memory reference base addresses.
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for (ScopStmt *Stmt : *S) {
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for (ScopStmt *Stmt : *S) {
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for (MemoryAccess *MA : *Stmt) {
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for (MemoryAccess *MA : *Stmt) {
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Value *BaseAddr = const_cast<Value *>(MA->getBaseAddr());
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Value *BaseAddr = MA->getBaseAddr();
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Values.insert((BaseAddr));
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Values.insert((BaseAddr));
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// FIXME: we assume that there is one and only one array to be written
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// FIXME: we assume that there is one and only one array to be written
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