forked from OSchip/llvm-project
[DAG] Defer merge store cycle checking to just before merge. NFCI.
llvm-svn: 332489
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@ -13473,14 +13473,6 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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continue;
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}
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// Check that we can merge these candidates without causing a cycle
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if (!checkMergeStoreCandidatesForDependencies(StoreNodes,
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NumConsecutiveStores)) {
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StoreNodes.erase(StoreNodes.begin(),
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StoreNodes.begin() + NumConsecutiveStores);
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continue;
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}
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// The node with the lowest store address.
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LLVMContext &Context = *DAG.getContext();
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const DataLayout &DL = DAG.getDataLayout();
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@ -13576,6 +13568,12 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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continue;
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}
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// Check that we can merge these candidates without causing a cycle.
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if (!checkMergeStoreCandidatesForDependencies(StoreNodes, NumElem)) {
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StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem);
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continue;
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}
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bool Merged = MergeStoresOfConstantsOrVecElts(
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StoreNodes, MemVT, NumElem, true, UseVector, LastIntegerTrunc);
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RV |= Merged;
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@ -13634,6 +13632,14 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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continue;
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}
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// Check that we can merge these candidates without causing a cycle.
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if (!checkMergeStoreCandidatesForDependencies(StoreNodes,
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NumStoresToMerge)) {
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StoreNodes.erase(StoreNodes.begin(),
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StoreNodes.begin() + NumStoresToMerge);
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continue;
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}
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bool Merged = MergeStoresOfConstantsOrVecElts(
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StoreNodes, MemVT, NumStoresToMerge, false, true, false);
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if (!Merged) {
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@ -13803,6 +13809,12 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
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continue;
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}
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// Check that we can merge these candidates without causing a cycle.
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if (!checkMergeStoreCandidatesForDependencies(StoreNodes, NumElem)) {
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StoreNodes.erase(StoreNodes.begin(), StoreNodes.begin() + NumElem);
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continue;
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}
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// Find if it is better to use vectors or integers to load and store
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// to memory.
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EVT JointMemOpVT;
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