forked from OSchip/llvm-project
[ARM] Allow rounding intrinsics to be tail predicated
This patch stops the trunc, rint, round, floor and ceil intrinsics from blocking tail predication. Differential Revision: https://reviews.llvm.org/D82553
This commit is contained in:
parent
8ba4867c27
commit
d9cb811cbf
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@ -84,6 +84,7 @@ class MVETailPredication : public LoopPass {
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DominatorTree *DT = nullptr;
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ScalarEvolution *SE = nullptr;
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TargetTransformInfo *TTI = nullptr;
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const ARMSubtarget *ST = nullptr;
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TargetLibraryInfo *TLI = nullptr;
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bool ClonedVCTPInExitBlock = false;
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@ -170,7 +171,7 @@ bool MVETailPredication::runOnLoop(Loop *L, LPPassManager&) {
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Function &F = *L->getHeader()->getParent();
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auto &TPC = getAnalysis<TargetPassConfig>();
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auto &TM = TPC.getTM<TargetMachine>();
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auto *ST = &TM.getSubtarget<ARMSubtarget>(F);
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ST = &TM.getSubtarget<ARMSubtarget>(F);
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DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
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LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
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TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
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@ -268,10 +269,18 @@ bool MVETailPredication::IsPredicatedVectorLoop() {
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case Intrinsic::get_active_lane_mask:
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ActiveLaneMask = true;
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LLVM_FALLTHROUGH;
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case Intrinsic::fma:
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case Intrinsic::sadd_sat:
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case Intrinsic::uadd_sat:
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continue;
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case Intrinsic::fma:
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case Intrinsic::trunc:
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case Intrinsic::rint:
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case Intrinsic::round:
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case Intrinsic::floor:
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case Intrinsic::ceil:
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if (ST->hasMVEFloatOps())
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continue;
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LLVM_FALLTHROUGH;
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default:
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break;
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}
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@ -0,0 +1,318 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -disable-mve-tail-predication=false -o - %s | FileCheck %s
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define arm_aapcs_vfpcc void @round(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 {
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; CHECK-LABEL: round:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK-NEXT: .LBB0_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vrinta.f32 q0, q0
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; CHECK-NEXT: vstrw.32 q0, [r1], #16
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; CHECK-NEXT: letp lr, .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp5 = icmp eq i32 %n, 0
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br i1 %cmp5, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %n, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %n, -1
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr float, float* %pSrcA, i32 %index
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%next.gep14 = getelementptr float, float* %pDst, i32 %index
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1)
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%0 = bitcast float* %next.gep to <4 x float>*
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%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
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%1 = call fast <4 x float> @llvm.round.v4f32(<4 x float> %wide.masked.load)
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%2 = bitcast float* %next.gep14 to <4 x float>*
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call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
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%index.next = add i32 %index, 4
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%3 = icmp eq i32 %index.next, %n.vec
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br i1 %3, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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define arm_aapcs_vfpcc void @rint(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 {
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; CHECK-LABEL: rint:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK-NEXT: .LBB1_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vrintx.f32 q0, q0
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; CHECK-NEXT: vstrw.32 q0, [r1], #16
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; CHECK-NEXT: letp lr, .LBB1_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp5 = icmp eq i32 %n, 0
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br i1 %cmp5, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %n, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %n, -1
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr float, float* %pSrcA, i32 %index
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%next.gep14 = getelementptr float, float* %pDst, i32 %index
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1)
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%0 = bitcast float* %next.gep to <4 x float>*
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%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
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%1 = call fast <4 x float> @llvm.rint.v4f32(<4 x float> %wide.masked.load)
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%2 = bitcast float* %next.gep14 to <4 x float>*
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call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
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%index.next = add i32 %index, 4
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%3 = icmp eq i32 %index.next, %n.vec
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br i1 %3, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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define arm_aapcs_vfpcc void @trunc(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 {
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; CHECK-LABEL: trunc:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK-NEXT: .LBB2_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vrintz.f32 q0, q0
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; CHECK-NEXT: vstrw.32 q0, [r1], #16
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; CHECK-NEXT: letp lr, .LBB2_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp5 = icmp eq i32 %n, 0
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br i1 %cmp5, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %n, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %n, -1
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr float, float* %pSrcA, i32 %index
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%next.gep14 = getelementptr float, float* %pDst, i32 %index
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1)
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%0 = bitcast float* %next.gep to <4 x float>*
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%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
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%1 = call fast <4 x float> @llvm.trunc.v4f32(<4 x float> %wide.masked.load)
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%2 = bitcast float* %next.gep14 to <4 x float>*
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call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
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%index.next = add i32 %index, 4
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%3 = icmp eq i32 %index.next, %n.vec
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br i1 %3, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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define arm_aapcs_vfpcc void @ceil(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 {
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; CHECK-LABEL: ceil:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK-NEXT: .LBB3_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vrintp.f32 q0, q0
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; CHECK-NEXT: vstrw.32 q0, [r1], #16
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; CHECK-NEXT: letp lr, .LBB3_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp5 = icmp eq i32 %n, 0
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br i1 %cmp5, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %n, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %n, -1
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr float, float* %pSrcA, i32 %index
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%next.gep14 = getelementptr float, float* %pDst, i32 %index
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1)
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%0 = bitcast float* %next.gep to <4 x float>*
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%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
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%1 = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> %wide.masked.load)
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%2 = bitcast float* %next.gep14 to <4 x float>*
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call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
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%index.next = add i32 %index, 4
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%3 = icmp eq i32 %index.next, %n.vec
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br i1 %3, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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define arm_aapcs_vfpcc void @floor(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 {
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; CHECK-LABEL: floor:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: dlstp.32 lr, r2
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; CHECK-NEXT: .LBB4_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrw.u32 q0, [r0], #16
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; CHECK-NEXT: vrintm.f32 q0, q0
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; CHECK-NEXT: vstrw.32 q0, [r1], #16
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; CHECK-NEXT: letp lr, .LBB4_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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entry:
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%cmp5 = icmp eq i32 %n, 0
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br i1 %cmp5, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %n, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %n, -1
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr float, float* %pSrcA, i32 %index
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%next.gep14 = getelementptr float, float* %pDst, i32 %index
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%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1)
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%0 = bitcast float* %next.gep to <4 x float>*
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%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
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%1 = call fast <4 x float> @llvm.floor.v4f32(<4 x float> %wide.masked.load)
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%2 = bitcast float* %next.gep14 to <4 x float>*
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call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
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%index.next = add i32 %index, 4
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%3 = icmp eq i32 %index.next, %n.vec
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br i1 %3, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup: ; preds = %vector.body, %entry
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ret void
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}
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; nearbyint shouldn't be tail predicated because it's lowered into multiple instructions
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define arm_aapcs_vfpcc void @nearbyint(float* noalias nocapture readonly %pSrcA, float* noalias nocapture %pDst, i32 %n) #0 {
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; CHECK-LABEL: nearbyint:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: it eq
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; CHECK-NEXT: popeq {r7, pc}
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; CHECK-NEXT: adds r3, r2, #3
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; CHECK-NEXT: bic r3, r3, #3
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; CHECK-NEXT: sub.w r12, r3, #4
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; CHECK-NEXT: movs r3, #1
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; CHECK-NEXT: add.w lr, r3, r12, lsr #2
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; CHECK-NEXT: adr r3, .LCPI5_0
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; CHECK-NEXT: sub.w r12, r2, #1
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; CHECK-NEXT: vldrw.u32 q0, [r3]
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: vdup.32 q1, r12
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; CHECK-NEXT: dls lr, lr
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; CHECK-NEXT: .LBB5_1: @ %vector.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vadd.i32 q2, q0, r2
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; CHECK-NEXT: vdup.32 q3, r2
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; CHECK-NEXT: vcmp.u32 hi, q3, q2
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; CHECK-NEXT: adds r2, #4
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpstt
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; CHECK-NEXT: vcmpt.u32 cs, q1, q2
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; CHECK-NEXT: vldrwt.u32 q2, [r0], #16
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; CHECK-NEXT: vrintr.f32 s15, s11
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; CHECK-NEXT: vrintr.f32 s14, s10
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; CHECK-NEXT: vrintr.f32 s13, s9
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; CHECK-NEXT: vrintr.f32 s12, s8
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vstrwt.32 q3, [r1], #16
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; CHECK-NEXT: le lr, .LBB5_1
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; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.3:
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; CHECK-NEXT: .LCPI5_0:
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 2 @ 0x2
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; CHECK-NEXT: .long 3 @ 0x3
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entry:
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%cmp5 = icmp eq i32 %n, 0
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br i1 %cmp5, label %for.cond.cleanup, label %vector.ph
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vector.ph: ; preds = %entry
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%n.rnd.up = add i32 %n, 3
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%n.vec = and i32 %n.rnd.up, -4
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%trip.count.minus.1 = add i32 %n, -1
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%next.gep = getelementptr float, float* %pSrcA, i32 %index
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%next.gep14 = getelementptr float, float* %pDst, i32 %index
|
||||
%active.lane.mask = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %index, i32 %trip.count.minus.1)
|
||||
%0 = bitcast float* %next.gep to <4 x float>*
|
||||
%wide.masked.load = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %0, i32 4, <4 x i1> %active.lane.mask, <4 x float> undef)
|
||||
%1 = call fast <4 x float> @llvm.nearbyint.v4f32(<4 x float> %wide.masked.load)
|
||||
%2 = bitcast float* %next.gep14 to <4 x float>*
|
||||
call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %1, <4 x float>* %2, i32 4, <4 x i1> %active.lane.mask)
|
||||
%index.next = add i32 %index, 4
|
||||
%3 = icmp eq i32 %index.next, %n.vec
|
||||
br i1 %3, label %for.cond.cleanup, label %vector.body
|
||||
|
||||
for.cond.cleanup: ; preds = %vector.body, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2
|
||||
|
||||
declare <4 x float> @llvm.trunc.v4f32(<4 x float>) #3
|
||||
|
||||
declare <4 x float> @llvm.rint.v4f32(<4 x float>) #3
|
||||
|
||||
declare <4 x float> @llvm.round.v4f32(<4 x float>) #3
|
||||
|
||||
declare <4 x float> @llvm.ceil.v4f32(<4 x float>) #3
|
||||
|
||||
declare <4 x float> @llvm.floor.v4f32(<4 x float>) #3
|
||||
|
||||
declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) #1
|
||||
|
||||
declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>) #4
|
Loading…
Reference in New Issue