forked from OSchip/llvm-project
Revert "[MachineCopyPropagation] Remove redundant copies after TailDup via machine-cp"
This reverts commit 371359. I'm suspecting a miscompile, I posted a reproducer to https://reviews.llvm.org/D65267. llvm-svn: 371421
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@ -68,7 +68,6 @@ using namespace llvm;
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STATISTIC(NumDeletes, "Number of dead copies deleted");
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STATISTIC(NumDeletes, "Number of dead copies deleted");
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STATISTIC(NumCopyForwards, "Number of copy uses forwarded");
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STATISTIC(NumCopyForwards, "Number of copy uses forwarded");
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STATISTIC(NumCopyBackwardPropagated, "Number of copy defs backward propagated");
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DEBUG_COUNTER(FwdCounter, "machine-cp-fwd",
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DEBUG_COUNTER(FwdCounter, "machine-cp-fwd",
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"Controls which register COPYs are forwarded");
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"Controls which register COPYs are forwarded");
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@ -212,13 +211,11 @@ private:
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void ReadRegister(unsigned Reg, MachineInstr &Reader,
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void ReadRegister(unsigned Reg, MachineInstr &Reader,
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DebugType DT);
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DebugType DT);
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void CopyPropagateBlock(MachineBasicBlock &MBB);
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void CopyPropagateBlock(MachineBasicBlock &MBB);
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bool eraseIfRedundant(MachineInstr &Copy);
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bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
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bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
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void forwardUses(MachineInstr &MI);
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void forwardUses(MachineInstr &MI);
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bool isForwardableRegClassCopy(const MachineInstr &Copy,
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bool isForwardableRegClassCopy(const MachineInstr &Copy,
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const MachineInstr &UseI, unsigned UseIdx);
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const MachineInstr &UseI, unsigned UseIdx);
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bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);
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bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);
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bool isSafeBackwardCopyPropagation(MachineInstr &Copy, MachineInstr &SrcMI);
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/// Candidates for deletion.
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/// Candidates for deletion.
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SmallSetVector<MachineInstr *, 8> MaybeDeadCopies;
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SmallSetVector<MachineInstr *, 8> MaybeDeadCopies;
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@ -277,57 +274,6 @@ static bool isNopCopy(const MachineInstr &PreviousCopy, unsigned Src,
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return SubIdx == TRI->getSubRegIndex(PreviousDef, Def);
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return SubIdx == TRI->getSubRegIndex(PreviousDef, Def);
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}
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}
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bool MachineCopyPropagation::isSafeBackwardCopyPropagation(
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MachineInstr &Copy, MachineInstr &SrcMI) {
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MachineOperand &SrcOp = SrcMI.getOperand(0);
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if (!(SrcOp.isReg() && SrcOp.isDef() &&
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SrcOp.getReg() == Copy.getOperand(1).getReg() && SrcOp.isRenamable() &&
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!SrcOp.isTied() && !SrcOp.isImplicit() &&
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!MRI->isReserved(SrcOp.getReg())))
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return false;
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if (const TargetRegisterClass *URC = SrcMI.getRegClassConstraint(0, TII, TRI))
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return URC->contains(Copy.getOperand(0).getReg());
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return false;
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}
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/// In a terminal BB, remove instruction \p Copy if \p Copy's src and dst are
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/// not used or defined between \p Copy and definition point of \p Copy's src.
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/// \p Copy's dst will be backward propagated to where \p Copy's src is defined.
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bool MachineCopyPropagation::eraseIfRedundant(MachineInstr &Copy) {
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// Only take terminal BBs into account.
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if (!Copy.getParent()->succ_empty())
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return false;
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if (!Copy.getOperand(1).isRenamable() || !Copy.getOperand(1).isKill())
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return false;
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unsigned Def = Copy.getOperand(0).getReg();
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unsigned Src = Copy.getOperand(1).getReg();
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if (MRI->isReserved(Src) || MRI->isReserved(Def))
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return false;
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MachineBasicBlock::reverse_iterator E = Copy.getParent()->rend(), It = Copy;
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It++;
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MachineInstr *SrcMI = nullptr;
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for (; It != E; ++It) {
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if (It->readsRegister(Src, TRI) || It->readsRegister(Def, TRI))
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return false;
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if (It->modifiesRegister(Def, TRI))
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return false;
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if (It->modifiesRegister(Src, TRI)) {
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SrcMI = &*It;
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break;
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}
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}
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if (!SrcMI)
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return false;
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if (!isSafeBackwardCopyPropagation(Copy, *SrcMI))
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return false;
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SrcMI->getOperand(0).setReg(Def);
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SrcMI->getOperand(0).setIsRenamable(Copy.getOperand(0).isRenamable());
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Copy.eraseFromParent();
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++NumCopyBackwardPropagated;
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++NumDeletes;
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return true;
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}
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/// Remove instruction \p Copy if there exists a previous copy that copies the
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/// Remove instruction \p Copy if there exists a previous copy that copies the
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/// register \p Src to the register \p Def; This may happen indirectly by
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/// register \p Src to the register \p Def; This may happen indirectly by
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/// copying the super registers.
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/// copying the super registers.
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@ -529,17 +475,6 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
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!Register::isVirtualRegister(Src) &&
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!Register::isVirtualRegister(Src) &&
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"MachineCopyPropagation should be run after register allocation!");
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"MachineCopyPropagation should be run after register allocation!");
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// In a terminal BB,
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// $reg0 = OP ...
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// ... <<< No uses of $reg0 and $reg1, no defs of $reg0 and $reg1
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// $reg1 = COPY $reg0 <<< $reg0 is killed
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// =>
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// $reg1 = OP ...
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// ...
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// <RET>
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if (eraseIfRedundant(*MI))
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continue;
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// The two copies cancel out and the source of the first copy
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// The two copies cancel out and the source of the first copy
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// hasn't been overridden, eliminate the second one. e.g.
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// hasn't been overridden, eliminate the second one. e.g.
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// %ecx = COPY %eax
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// %ecx = COPY %eax
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@ -26,7 +26,8 @@ define dso_local i1 @t(%class.A* %this, i32 %color, i32 %vertex) local_unnamed_a
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; CHECK-P9-NEXT: cmplwi r3, 2
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; CHECK-P9-NEXT: cmplwi r3, 2
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; CHECK-P9-NEXT: bge- cr0, .LBB0_6
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; CHECK-P9-NEXT: bge- cr0, .LBB0_6
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; CHECK-P9-NEXT: # %bb.3: # %land.lhs.true.1
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; CHECK-P9-NEXT: # %bb.3: # %land.lhs.true.1
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; CHECK-P9-NEXT: li r3, 0
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; CHECK-P9-NEXT: li r5, 0
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; CHECK-P9-NEXT: mr r3, r5
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; CHECK-P9-NEXT: blr
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; CHECK-P9-NEXT: blr
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; CHECK-P9-NEXT: .LBB0_4: # %lor.lhs.false
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; CHECK-P9-NEXT: .LBB0_4: # %lor.lhs.false
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; CHECK-P9-NEXT: cmplwi cr0, r4, 0
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; CHECK-P9-NEXT: cmplwi cr0, r4, 0
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@ -153,8 +153,9 @@ define void @test_512(i512* %a, i512* %b, i512* %out) nounwind {
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; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; X32-NEXT: adcl $0, %edx
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; X32-NEXT: adcl $0, %edx
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; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl 8(%ecx), %ebx
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; X32-NEXT: movl %esi, %ecx
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; X32-NEXT: movl 8(%esi), %ebx
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; X32-NEXT: movl %ebx, %eax
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; X32-NEXT: movl %ebx, %eax
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; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; X32-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
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; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
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@ -98,8 +98,8 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
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; X86-NEXT: addl %esi, %ecx
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; X86-NEXT: addl %esi, %ecx
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; X86-NEXT: adcl $0, %ebp
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; X86-NEXT: adcl $0, %ebp
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: mull %edx
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; X86-NEXT: mull %esi
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; X86-NEXT: movl %edx, %esi
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; X86-NEXT: movl %edx, %esi
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; X86-NEXT: addl %ecx, %eax
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; X86-NEXT: addl %ecx, %eax
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; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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