From d9a99ce53d7d84aad8f7019b4628020f51046f25 Mon Sep 17 00:00:00 2001 From: Bradley Smith Date: Fri, 15 Jan 2016 10:25:14 +0000 Subject: [PATCH] [ARM] Add MOVW/MOVT instructions to ARMv8-M Baseline/Mainline llvm-svn: 257879 --- llvm/lib/Target/ARM/ARMInstrThumb2.td | 17 +++++++----- llvm/lib/Target/ARM/ARMSubtarget.cpp | 2 +- .../ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 8 +++--- llvm/test/CodeGen/ARM/movt.ll | 6 +++-- llvm/test/MC/ARM/thumb-movwt-reloc.s | 27 +++++++++++++++++++ llvm/test/MC/ARM/thumbv8m.s | 8 ++++++ 6 files changed, 54 insertions(+), 14 deletions(-) create mode 100644 llvm/test/MC/ARM/thumb-movwt-reloc.s diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index e6533a321e72..176752705486 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -1906,7 +1906,8 @@ def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, "movw", "\t$Rd, $imm", - [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> { + [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>, + Requires<[IsThumb, HasV8MBaseline]> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24-21} = 0b0010; @@ -1924,8 +1925,9 @@ def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, let DecoderMethod = "DecodeT2MOVTWInstruction"; } -def : t2InstAlias<"mov${p} $Rd, $imm", - (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>; +def : InstAlias<"mov${p} $Rd, $imm", + (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>, + Requires<[IsThumb, HasV8MBaseline]>; def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; @@ -1936,7 +1938,8 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd), "movt", "\t$Rd, $imm", [(set rGPR:$Rd, (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>, - Sched<[WriteALU]> { + Sched<[WriteALU]>, + Requires<[IsThumb, HasV8MBaseline]> { let Inst{31-27} = 0b11110; let Inst{25} = 1; let Inst{24-21} = 0b0110; @@ -1956,7 +1959,7 @@ def t2MOVTi16 : T2I<(outs rGPR:$Rd), def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>, - Sched<[WriteALU]>; + Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>; } // Constraints def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>; @@ -3879,7 +3882,7 @@ let isReMaterializable = 1 in { def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), IIC_iMOVix2addpc, [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, - Requires<[IsThumb2, UseMovt]>; + Requires<[IsThumb, HasV8MBaseline, UseMovt]>; } @@ -3893,7 +3896,7 @@ def : T2Pat<(ARMWrapper tglobaltlsaddr:$dst), // ConstantPool, GlobalAddress, and JumpTable def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, - Requires<[IsThumb2, UseMovt]>; + Requires<[IsThumb, HasV8MBaseline, UseMovt]>; def : T2Pat<(ARMWrapperJT tjumptable:$dst), (t2LEApcrelJT tjumptable:$dst)>; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index bcffee137344..2a94116a7e2f 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -350,7 +350,7 @@ bool ARMSubtarget::useMovt(const MachineFunction &MF) const { // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit // immediates as it is inherently position independent, and may be out of // range otherwise. - return !NoMovt && hasV6T2Ops() && + return !NoMovt && hasV8MBaselineOps() && (isTargetWindows() || !MF.getFunction()->optForMinSize()); } diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index b88578309f08..84638bc06675 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -1049,12 +1049,12 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, switch (ARM16Expr->getKind()) { default: llvm_unreachable("Unsupported ARMFixup"); case ARMMCExpr::VK_ARM_HI16: - Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movt_hi16 - : ARM::fixup_arm_movt_hi16); + Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16 + : ARM::fixup_arm_movt_hi16); break; case ARMMCExpr::VK_ARM_LO16: - Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movw_lo16 - : ARM::fixup_arm_movw_lo16); + Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16 + : ARM::fixup_arm_movw_lo16); break; } diff --git a/llvm/test/CodeGen/ARM/movt.ll b/llvm/test/CodeGen/ARM/movt.ll index 94c022ee2712..da9b698f2099 100644 --- a/llvm/test/CodeGen/ARM/movt.ll +++ b/llvm/test/CodeGen/ARM/movt.ll @@ -1,9 +1,11 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s ; rdar://7317664 +; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s + define i32 @t(i32 %X) nounwind { ; CHECK-LABEL: t: -; CHECK: movt r0, #65535 +; CHECK: movt r{{[0-9]}}, #65535 entry: %0 = or i32 %X, -65536 ret i32 %0 @@ -11,7 +13,7 @@ entry: define i32 @t2(i32 %X) nounwind { ; CHECK-LABEL: t2: -; CHECK: movt r0, #65534 +; CHECK: movt r{{[0-9]}}, #65534 entry: %0 = or i32 %X, -131072 %1 = and i32 %0, -65537 diff --git a/llvm/test/MC/ARM/thumb-movwt-reloc.s b/llvm/test/MC/ARM/thumb-movwt-reloc.s new file mode 100644 index 000000000000..c00cf1c1c9e0 --- /dev/null +++ b/llvm/test/MC/ARM/thumb-movwt-reloc.s @@ -0,0 +1,27 @@ +@ RUN: llvm-mc -triple thumbv8m.base-eabi -filetype asm -o - %s | FileCheck %s +@ RUN: llvm-mc -triple thumbv8m.base-eabi -filetype obj -o - %s | llvm-readobj -r \ +@ RUN: | FileCheck -check-prefix CHECK-RELOCATIONS %s + + .syntax unified + + .type function,%function +function: + bx lr + + .global external + .type external,%function + + .type test,%function +test: + movw r0, :lower16:function + movt r0, :upper16:function + +@ CHECK-LABEL: test: +@ CHECK: movw r0, :lower16:function +@ CHECK: movt r0, :upper16:function + +@ CHECK-RELOCATIONS: Relocations [ +@ CHECK-RELOCATIONS: 0x2 R_ARM_THM_MOVW_ABS_NC function 0x0 +@ CHECK-RELOCATIONS: 0x6 R_ARM_THM_MOVT_ABS function 0x0 +@ CHECK-RELOCATIONS: ] + diff --git a/llvm/test/MC/ARM/thumbv8m.s b/llvm/test/MC/ARM/thumbv8m.s index 8a76ae7776e6..0127ca8b8452 100644 --- a/llvm/test/MC/ARM/thumbv8m.s +++ b/llvm/test/MC/ARM/thumbv8m.s @@ -20,3 +20,11 @@ mov.w r0, r0 // CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f] isb sy + +// 'XO generation' + +// CHECK: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71] +movw r1, #0xffff + +// CHECK: movt r1, #65535 @ encoding: [0xcf,0xf6,0xff,0x71] +movt r1, #0xffff