forked from OSchip/llvm-project
[mips] Guard all short instructions correctly.
Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47533 llvm-svn: 333645
This commit is contained in:
Simon Dardis
parent
ac804c2238
commit
d9a453832d
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@ -1692,6 +1692,14 @@ def : MipsInstAlias<"negu $rt, $rs",
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def : MipsInstAlias<"negu $rt",
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(SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
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ISA_MICROMIPS32R6;
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def : MipsInstAlias<"beqz16 $rs, $offset", (BEQZC16_MMR6 GPRMM16Opnd:$rs,
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brtarget7_mm:$offset),
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0>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"bnez16 $rs, $offset", (BNEZC16_MMR6 GPRMM16Opnd:$rs,
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brtarget7_mm:$offset),
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0>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"b16 $offset", (BC16_MMR6 brtarget10_mm:$offset), 0>,
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ISA_MICROMIPS32R6;
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//===----------------------------------------------------------------------===//
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//
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@ -636,48 +636,58 @@ let FastISelShouldIgnore = 1 in {
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LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
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}
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def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
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mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
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mem_mm_4>, LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;
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def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
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mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>;
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mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;
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def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
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LOAD_STORE_FM_MM16<0x1a>;
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LOAD_STORE_FM_MM16<0x1a>, ISA_MICROMIPS;
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def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
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II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>;
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II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
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II_SH, mem_mm_4_lsl1>,
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LOAD_STORE_FM_MM16<0x2a>;
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LOAD_STORE_FM_MM16<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
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mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>;
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mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
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LOAD_GP_FM_MM16<0x19>;
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LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
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def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
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LOAD_STORE_SP_FM_MM16<0x12>;
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LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;
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def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
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LOAD_STORE_SP_FM_MM16<0x32>;
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def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
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def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
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def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
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def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
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LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,
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ISA_MICROMIPS;
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def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16,
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ISA_MICROMIPS;
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def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16,
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ISA_MICROMIPS;
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def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16, ISA_MICROMIPS;
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def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,
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MFHILO_FM_MM16<0x10>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,
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MFHILO_FM_MM16<0x12>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
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def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
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IsAsCheapAsAMove;
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IsAsCheapAsAMove, ISA_MICROMIPS32_NOT_MIPS32R6;
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def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
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def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>;
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def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>;
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def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>;
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def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
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BEQNEZ_FM_MM16<0x23>;
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BEQNEZ_FM_MM16<0x23>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
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BEQNEZ_FM_MM16<0x2b>;
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def B16_MM : UncondBranchMM16<"b16">, B16_FM;
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BEQNEZ_FM_MM16<0x2b>, ISA_MICROMIPS32_NOT_MIPS32R6;
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def B16_MM : UncondBranchMM16<"b16">, B16_FM, ISA_MICROMIPS32_NOT_MIPS32R6;
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def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
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ISA_MICROMIPS32_NOT_MIPS32R6;
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def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
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@ -5,8 +5,8 @@
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# RUN: | llvm-objdump -d -mattr=micromips - | FileCheck %s
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# CHECK: 0: 8f 7e beqzc16 $6, -4
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# CHECK: 6: cf fe bc16 -4
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# CHECK: c: b7 ff ff fe balc -4
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# CHECK: 2: cf fe bc16 -4
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# CHECK: 4: b7 ff ff fe balc -4
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beqz16 $6, -4
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b16 -4
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@ -2,53 +2,99 @@
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.set noat
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addiusp -16 # CHECK: addiusp -16 # encoding: [0x4f,0xf9]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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addiusp -1028 # CHECK: addiusp -1028 # encoding: [0x4f,0xff]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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addiusp -1032 # CHECK: addiusp -1032 # encoding: [0x4f,0xfd]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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addiusp 1024 # CHECK: addiusp 1024 # encoding: [0x4c,0x01]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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addiusp 1028 # CHECK: addiusp 1028 # encoding: [0x4c,0x03]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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andi16 $16, $2, 31 # CHECK: andi16 $16, $2, 31 # encoding: [0x2c,0x29]
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# CHECK: # <MCInst #{{.*}} ANDI16_MM
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jraddiusp 20 # CHECK: jraddiusp 20 # encoding: [0x47,0x05]
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# CHECK: # <MCInst #{{.*}} JRADDIUSP
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addu16 $6, $17, $4 # CHECK: addu16 $6, $17, $4 # encoding: [0x07,0x42]
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# CHECK: # <MCInst #{{.*}} ADDU16_MM
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subu16 $5, $16, $3 # CHECK: subu16 $5, $16, $3 # encoding: [0x06,0xb1]
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# CHECK: # <MCInst #{{.*}} SUBU16_MM
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and16 $16, $2 # CHECK: and16 $16, $2 # encoding: [0x44,0x82]
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# CHECK: # <MCInst #{{.*}} AND16_MM
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not16 $17, $3 # CHECK: not16 $17, $3 # encoding: [0x44,0x0b]
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# CHECK: # <MCInst #{{.*}} NOT16_MM
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or16 $16, $4 # CHECK: or16 $16, $4 # encoding: [0x44,0xc4]
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# CHECK: # <MCInst #{{.*}} OR16_MM
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xor16 $17, $5 # CHECK: xor16 $17, $5 # encoding: [0x44,0x4d]
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# CHECK: # <MCInst #{{.*}} XOR16_MM
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sll16 $3, $16, 5 # CHECK: sll16 $3, $16, 5 # encoding: [0x25,0x8a]
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# CHECK: # <MCInst #{{.*}} SLL16_MM
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srl16 $4, $17, 6 # CHECK: srl16 $4, $17, 6 # encoding: [0x26,0x1d]
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# CHECK: # <MCInst #{{.*}} SRL16_MM
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lbu16 $3, 4($17) # CHECK: lbu16 $3, 4($17) # encoding: [0x09,0x94]
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# CHECK: # <MCInst #{{.*}} LBU16_MM
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lbu16 $3, -1($16) # CHECK: lbu16 $3, -1($16) # encoding: [0x09,0x8f]
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# CHECK: # <MCInst #{{.*}} LBU16_MM
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lhu16 $3, 4($16) # CHECK: lhu16 $3, 4($16) # encoding: [0x29,0x82]
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# CHECK: # <MCInst #{{.*}} LHU16_MM
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lw16 $4, 8($17) # CHECK: lw16 $4, 8($17) # encoding: [0x6a,0x12]
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# CHECK: # <MCInst #{{.*}} LW16_MM
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sb16 $3, 4($16) # CHECK: sb16 $3, 4($16) # encoding: [0x89,0x84]
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# CHECK: # <MCInst #{{.*}} SB16_MM
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sh16 $4, 8($17) # CHECK: sh16 $4, 8($17) # encoding: [0xaa,0x14]
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# CHECK: # <MCInst #{{.*}} SH16_MM
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sw16 $4, 4($17) # CHECK: sw16 $4, 4($17) # encoding: [0xea,0x11]
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# CHECK: # <MCInst #{{.*}} SW16_MM
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sw16 $zero, 4($17) # CHECK: sw16 $zero, 4($17) # encoding: [0xe8,0x11]
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# CHECK: # <MCInst #{{.*}} SW16_MM
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mfhi16 $9 # CHECK: mfhi16 $9 # encoding: [0x46,0x09]
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# CHECK: # <MCInst #{{.*}} MFHI16_MM
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mflo16 $9 # CHECK: mflo16 $9 # encoding: [0x46,0x49]
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# CHECK: # <MCInst #{{.*}} MFLO16_MM
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move $25, $1 # CHECK: move $25, $1 # encoding: [0x0f,0x21]
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# CHECK: # <MCInst #{{.*}} MOVE16_MM
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jrc $9 # CHECK: jrc $9 # encoding: [0x45,0xa9]
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# CHECK: # <MCInst #{{.*}} JRC16_MM
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jalr $9 # CHECK: jalr $9 # encoding: [0x45,0xc9]
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# CHECK: # <MCInst #{{.*}} JALR16_MM
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jalrs16 $9 # CHECK: jalrs16 $9 # encoding: [0x45,0xe9]
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# CHECK: # <MCInst #{{.*}} MOVE16_MM
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jr16 $9 # CHECK: jr16 $9 # encoding: [0x45,0x89]
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# CHECK: # <MCInst #{{.*}} JR16_MM
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li16 $3, -1 # CHECK: li16 $3, -1 # encoding: [0xed,0xff]
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# CHECK: # <MCInst #{{.*}} LI16_MM
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li16 $3, 126 # CHECK: li16 $3, 126 # encoding: [0xed,0xfe]
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# CHECK: # <MCInst #{{.*}} LI16_MM
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addiur1sp $7, 4 # CHECK: addiur1sp $7, 4 # encoding: [0x6f,0x83]
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# CHECK: # <MCInst #{{.*}} ADDIUR1SP_MM
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addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
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# CHECK: # <MCInst #{{.*}} ADDIUR2_MM
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addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
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# CHECK: # <MCInst #{{.*}} ADDIUR2_MM
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addius5 $7, -2 # CHECK: addius5 $7, -2 # encoding: [0x4c,0xfc]
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nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
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beqz16 $6, 20 # CHECK: beqz16 $6, 20 # encoding: [0x8f,0x0a]
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# CHECK: # <MCInst #{{.*}} BEQZ16_MM
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bnez16 $6, 20 # CHECK: bnez16 $6, 20 # encoding: [0xaf,0x0a]
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# CHECK: # <MCInst #{{.*}} BNEZ16_MM
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b16 132 # CHECK: b16 132 # encoding: [0xcc,0x42]
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# CHECK: # <MCInst #{{.*}} B16_MM
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lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12]
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# CHECK: # <MCInst #{{.*}} LWM16_MM
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swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52]
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movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
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break16 8 # CHECK: break16 8 # encoding: [0x46,0x88]
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sdbbp16 14 # CHECK: sdbbp16 14 # encoding: [0x46,0xce]
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lw $3, 32($sp) # CHECK: lw $3, 32($sp) # encoding: [0x48,0x68]
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sw $4, 124($sp) # CHECK: sw $4, 124($sp) # encoding: [0xc8,0x9f]
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lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
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# CHECK: # <MCInst #{{.*}} SWM16_MM
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movep $5, $6, $2, $3 # CHECK: movep $5, $6, $2, $3 # encoding: [0x84,0x34]
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# CHECK: # <MCInst #{{.*}} MOVEP_MM
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break16 8 # CHECK: break16 8 # encoding: [0x46,0x88]
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# CHECK: # <MCInst #{{.*}} BREAK16_MM
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sdbbp16 14 # CHECK: sdbbp16 14 # encoding: [0x46,0xce]
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# CHECK: # <MCInst #{{.*}} SDBBP16_MM
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lw $3, 32($sp) # CHECK: lw $3, 32($sp) # encoding: [0x48,0x68]
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# CHECK: # <MCInst #{{.*}} LWSP_MM
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sw $4, 124($sp) # CHECK: sw $4, 124($sp) # encoding: [0xc8,0x9f]
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# CHECK: # <MCInst #{{.*}} SWSP_MM
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lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
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# CHECK: # <MCInst #{{.*}} LWGP_MM
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abs.s $f0, $f2 # CHECK: abs.s $f0, $f2 # encoding: [0x54,0x02,0x03,0x7b]
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# CHECK-NEXT: # <MCInst #{{[0-9]+}} FABS_S_MM
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abs.d $f4, $f6 # CHECK: abs.d $f4, $f6 # encoding: [0x54,0x86,0x23,0x7b]
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@ -6,14 +6,23 @@
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addu $3, $4, $5 # CHECK: addu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x50]
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addiupc $4, 100 # CHECK: lapc $4, 100 # encoding: [0x78,0x80,0x00,0x19]
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addiur1sp $7, 4 # CHECK: addiur1sp $7, 4 # encoding: [0x6f,0x83]
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# CHECK: # <MCInst #{{.*}} ADDIUR1SP_MM
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addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
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# CHECK: # <MCInst #{{.*}} ADDIUR2_MM
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addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
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# CHECK: # <MCInst #{{.*}} ADDIUR2_MM
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addius5 $7, -2 # CHECK: addius5 $7, -2 # encoding: [0x4c,0xfc]
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# CHECK: # <MCInst #{{.*}} ADDIUS5_MM
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addiusp -1028 # CHECK: addiusp -1028 # encoding: [0x4f,0xff]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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addiusp -1032 # CHECK: addiusp -1032 # encoding: [0x4f,0xfd]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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addiusp 1024 # CHECK: addiusp 1024 # encoding: [0x4c,0x01]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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addiusp 1028 # CHECK: addiusp 1028 # encoding: [0x4c,0x03]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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addiusp -16 # CHECK: addiusp -16 # encoding: [0x4f,0xf9]
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# CHECK: # <MCInst #{{.*}} ADDIUSP_MM
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aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0x78,0x7f,0x00,0x38]
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and $3, $4, $5 # CHECK: and $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x50]
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andi $3, $4, 1234 # CHECK: andi $3, $4, 1234 # encoding: [0xd0,0x64,0x04,0xd2]
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@ -36,11 +45,15 @@
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bnezc $3, 64 # CHECK: bnezc $3, 64 # encoding: [0xa0,0x60,0x00,0x10]
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balc 7286128 # CHECK: balc 7286128 # encoding: [0xb4,0x37,0x96,0xb8]
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b 132 # CHECK: bc16 132 # encoding: [0xcc,0x42]
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# CHECK: # <MCInst #{{.*}} BC16_MMR6
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||||
bc 7286128 # CHECK: bc 7286128 # encoding: [0x94,0x37,0x96,0xb8]
|
||||
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC_MMR6
|
||||
# CHECK: # <MCInst #{{.*}} BC_MMR6
|
||||
bc16 132 # CHECK: bc16 132 # encoding: [0xcc,0x42]
|
||||
beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a]
|
||||
bnezc16 $6, 20 # CHECK: bnezc16 $6, 20 # encoding: [0xaf,0x0a]
|
||||
# CHECK: # <MCInst #{{.*}} BC16_MMR6
|
||||
beqzc16 $6, 20 # CHECK: beqzc16 $6, 20 # encoding: [0x8f,0x0a]
|
||||
# CHECK: # <MCInst #{{.*}} BEQZC16_MMR6
|
||||
bnezc16 $6, 20 # CHECK: bnezc16 $6, 20 # encoding: [0xaf,0x0a]
|
||||
# CHECK: # <MCInst #{{.*}} BNEZC16_MMR6
|
||||
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c]
|
||||
break # CHECK: break # encoding: [0x00,0x00,0x00,0x07]
|
||||
break 7 # CHECK: break 7 # encoding: [0x00,0x07,0x00,0x07]
|
||||
|
|
|
|||
Loading…
Reference in New Issue