forked from OSchip/llvm-project
AMDGPU/GlobalISel: Adjust image load register type based on dmask
Trim elements that won't be written. The equivalent still needs to be done for writes. Also start widening 3 elements to 4 elements. Selection will get the count from the dmask.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
83ffbf2618
commit
d9a012ed8a
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@ -3374,69 +3374,6 @@ bool AMDGPULegalizerInfo::legalizeBufferAtomic(MachineInstr &MI,
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return true;
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}
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// Produce a vector of s16 elements from s32 pieces.
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static void truncToS16Vector(MachineIRBuilder &B, Register DstReg,
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ArrayRef<Register> UnmergeParts) {
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const LLT S16 = LLT::scalar(16);
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SmallVector<Register, 4> RemergeParts(UnmergeParts.size());
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for (int I = 0, E = UnmergeParts.size(); I != E; ++I)
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RemergeParts[I] = B.buildTrunc(S16, UnmergeParts[I]).getReg(0);
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B.buildBuildVector(DstReg, RemergeParts);
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}
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/// Convert a set of s32 registers to a result vector with s16 elements.
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static void bitcastToS16Vector(MachineIRBuilder &B, Register DstReg,
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ArrayRef<Register> UnmergeParts) {
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MachineRegisterInfo &MRI = *B.getMRI();
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const LLT V2S16 = LLT::vector(2, 16);
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LLT TargetTy = MRI.getType(DstReg);
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int NumElts = UnmergeParts.size();
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if (NumElts == 1) {
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assert(TargetTy == V2S16);
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B.buildBitcast(DstReg, UnmergeParts[0]);
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return;
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}
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SmallVector<Register, 4> RemergeParts(NumElts);
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for (int I = 0; I != NumElts; ++I)
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RemergeParts[I] = B.buildBitcast(V2S16, UnmergeParts[I]).getReg(0);
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if (TargetTy.getSizeInBits() == 32u * NumElts) {
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B.buildConcatVectors(DstReg, RemergeParts);
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return;
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}
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const LLT V3S16 = LLT::vector(3, 16);
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const LLT V6S16 = LLT::vector(6, 16);
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// Widen to v6s16 and unpack v3 parts.
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assert(TargetTy == V3S16);
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RemergeParts.push_back(B.buildUndef(V2S16).getReg(0));
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auto Concat = B.buildConcatVectors(V6S16, RemergeParts);
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B.buildUnmerge({DstReg, MRI.createGenericVirtualRegister(V3S16)}, Concat);
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}
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// FIXME: Just vector trunc should be sufficent, but legalization currently
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// broken.
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static void repackUnpackedD16Load(MachineIRBuilder &B, Register DstReg,
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Register WideDstReg) {
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const LLT S32 = LLT::scalar(32);
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const LLT S16 = LLT::scalar(16);
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auto Unmerge = B.buildUnmerge(S32, WideDstReg);
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int NumOps = Unmerge->getNumOperands() - 1;
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SmallVector<Register, 4> RemergeParts(NumOps);
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for (int I = 0; I != NumOps; ++I)
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RemergeParts[I] = B.buildTrunc(S16, Unmerge.getReg(I)).getReg(0);
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B.buildBuildVector(DstReg, RemergeParts);
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}
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/// Turn a set of s16 typed registers in \p A16AddrRegs into a dword sized
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/// vector with s16 typed elements.
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static void packImageA16AddressToDwords(MachineIRBuilder &B,
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@ -3493,14 +3430,18 @@ static int getImageNumVAddr(const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr,
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return BaseOpcode->NumExtraArgs + NumGradients + NumCoords + NumLCM;
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}
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static int getDMaskIdx(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode,
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int NumDefs) {
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assert(!BaseOpcode->Atomic);
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return NumDefs + 1 + (BaseOpcode->Store ? 1 : 0);
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}
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/// Return first address operand index in an image intrinsic.
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static int getImageVAddrIdxBegin(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode,
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int NumDefs) {
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if (BaseOpcode->Atomic)
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return NumDefs + 1 + (BaseOpcode->AtomicX2 ? 2 : 1);
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int DMaskIdx = NumDefs + 1 + (BaseOpcode->Store ? 1 : 0);
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return DMaskIdx + 1;
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return getDMaskIdx(BaseOpcode, NumDefs) + 1;
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}
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/// Rewrite image intrinsics to use register layouts expected by the subtarget.
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@ -3544,6 +3485,7 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
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MachineRegisterInfo *MRI = B.getMRI();
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const LLT S32 = LLT::scalar(32);
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const LLT S16 = LLT::scalar(16);
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const LLT V2S16 = LLT::vector(2, 16);
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// Index of first address argument
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const int AddrIdx = getImageVAddrIdxBegin(BaseOpcode, NumDefs);
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@ -3603,10 +3545,15 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
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convertImageAddrToPacked(B, MI, DimIdx, NumVAddrs);
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}
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if (BaseOpcode->Atomic) // No d16 atomics, or TFE.
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return true;
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int DMaskLanes = 0;
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if (!BaseOpcode->Atomic) {
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const int DMaskIdx = getDMaskIdx(BaseOpcode, NumDefs);
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unsigned DMask = MI.getOperand(DMaskIdx).getImm();
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DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask);
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}
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if (BaseOpcode->Store) { // No TFE for stores?
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// TODO: Handle dmask trim
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Register VData = MI.getOperand(1).getReg();
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LLT Ty = MRI->getType(VData);
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if (!Ty.isVector() || Ty.getElementType() != S16)
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@ -3626,91 +3573,162 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
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LLT Ty = MRI->getType(DstReg);
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const LLT EltTy = Ty.getScalarType();
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const bool IsD16 = Ty.getScalarType() == S16;
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const unsigned NumElts = Ty.isVector() ? Ty.getNumElements() : 1;
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const int NumElts = Ty.isVector() ? Ty.getNumElements() : 1;
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// Confirm that the return type is large enough for the dmask specified
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if (NumElts < DMaskLanes)
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return false;
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if (NumElts > 4 || DMaskLanes > 4)
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return false;
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const unsigned AdjustedNumElts = DMaskLanes == 0 ? 1 : DMaskLanes;
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const LLT AdjustedTy = Ty.changeNumElements(AdjustedNumElts);
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// The raw dword aligned data component of the load. The only legal cases
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// where this matters should be when using the packed D16 format, for
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// s16 -> <2 x s16>, and <3 x s16> -> <4 x s16>,
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LLT RoundedTy;
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// S32 vector to to cover all data, plus TFE result element.
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LLT TFETy;
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// Register type to use for each loaded component. Will be S32 or V2S16.
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LLT RegTy;
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if (IsD16 && ST.hasUnpackedD16VMem()) {
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RoundedTy = LLT::scalarOrVector(AdjustedNumElts, 32);
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TFETy = LLT::vector(AdjustedNumElts + 1, 32);
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RegTy = S32;
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} else {
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unsigned EltSize = EltTy.getSizeInBits();
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unsigned RoundedElts = (AdjustedTy.getSizeInBits() + 31) / 32;
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unsigned RoundedSize = 32 * RoundedElts;
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RoundedTy = LLT::scalarOrVector(RoundedSize / EltSize, EltSize);
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TFETy = LLT::vector(RoundedSize / 32 + 1, S32);
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RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32;
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}
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// The return type does not need adjustment.
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// TODO: Should we change s16 case to s32 or <2 x s16>?
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if (!IsTFE && (RoundedTy == Ty || !Ty.isVector()))
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return true;
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Register Dst1Reg;
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// Insert after the instruction.
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B.setInsertPt(*MI.getParent(), ++MI.getIterator());
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// TODO: For TFE with d16, if we used a TFE type that was a multiple of <2 x
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// s16> instead of s32, we would only need 1 bitcast instead of multiple.
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const LLT LoadResultTy = IsTFE ? TFETy : RoundedTy;
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const int ResultNumRegs = LoadResultTy.getSizeInBits() / 32;
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Register NewResultReg = MRI->createGenericVirtualRegister(LoadResultTy);
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MI.getOperand(0).setReg(NewResultReg);
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// In the IR, TFE is supposed to be used with a 2 element struct return
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// type. The intruction really returns these two values in one contiguous
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// register, with one additional dword beyond the loaded data. Rewrite the
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// return type to use a single register result.
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if (IsTFE) {
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// In the IR, TFE is supposed to be used with a 2 element struct return
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// type. The intruction really returns these two values in one contiguous
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// register, with one additional dword beyond the loaded data. Rewrite the
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// return type to use a single register result.
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Register Dst1Reg = MI.getOperand(1).getReg();
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Dst1Reg = MI.getOperand(1).getReg();
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if (MRI->getType(Dst1Reg) != S32)
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return false;
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// TODO: Make sure the TFE operand bit is set.
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// The raw dword aligned data component of the load. The only legal cases
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// where this matters should be when using the packed D16 format, for
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// s16 -> <2 x s16>, and <3 x s16> -> <4 x s16>,
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LLT RoundedTy;
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LLT TFETy;
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if (IsD16 && ST.hasUnpackedD16VMem()) {
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RoundedTy = LLT::scalarOrVector(NumElts, 32);
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TFETy = LLT::vector(NumElts + 1, 32);
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} else {
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unsigned EltSize = Ty.getScalarSizeInBits();
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unsigned RoundedElts = (Ty.getSizeInBits() + 31) / 32;
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unsigned RoundedSize = 32 * RoundedElts;
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RoundedTy = LLT::scalarOrVector(RoundedSize / EltSize, EltSize);
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TFETy = LLT::vector(RoundedSize / 32 + 1, S32);
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}
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Register TFEReg = MRI->createGenericVirtualRegister(TFETy);
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MI.getOperand(0).setReg(TFEReg);
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MI.RemoveOperand(1);
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// Insert after the instruction.
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B.setInsertPt(*MI.getParent(), ++MI.getIterator());
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// Now figure out how to copy the new result register back into the old
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// result.
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SmallVector<Register, 5> UnmergeResults(TFETy.getNumElements(), Dst1Reg);
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int NumDataElts = TFETy.getNumElements() - 1;
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if (!Ty.isVector()) {
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// Simplest case is a trivial unmerge (plus a truncate for d16).
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UnmergeResults[0] = Ty == S32 ?
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DstReg : MRI->createGenericVirtualRegister(S32);
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B.buildUnmerge(UnmergeResults, TFEReg);
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if (Ty != S32)
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B.buildTrunc(DstReg, UnmergeResults[0]);
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// Handle the easy case that requires no repack instructions.
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if (Ty == S32) {
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B.buildUnmerge({DstReg, Dst1Reg}, NewResultReg);
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return true;
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}
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}
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// Now figure out how to copy the new result register back into the old
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// result.
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SmallVector<Register, 5> ResultRegs(ResultNumRegs, Dst1Reg);
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const int NumDataRegs = IsTFE ? ResultNumRegs - 1 : ResultNumRegs;
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if (ResultNumRegs == 1) {
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assert(!IsTFE);
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ResultRegs[0] = NewResultReg;
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} else {
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// We have to repack into a new vector of some kind.
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for (int I = 0; I != NumDataElts; ++I)
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UnmergeResults[I] = MRI->createGenericVirtualRegister(S32);
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B.buildUnmerge(UnmergeResults, TFEReg);
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for (int I = 0; I != NumDataRegs; ++I)
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ResultRegs[I] = MRI->createGenericVirtualRegister(RegTy);
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B.buildUnmerge(ResultRegs, NewResultReg);
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// Drop the final TFE element.
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ArrayRef<Register> DataPart(UnmergeResults.data(), NumDataElts);
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if (EltTy == S32)
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B.buildBuildVector(DstReg, DataPart);
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else if (ST.hasUnpackedD16VMem())
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truncToS16Vector(B, DstReg, DataPart);
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else
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bitcastToS16Vector(B, DstReg, DataPart);
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// Drop the final TFE element to get the data part. The TFE result is
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// directly written to the right place already.
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if (IsTFE)
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ResultRegs.resize(NumDataRegs);
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}
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// For an s16 scalar result, we form an s32 result with a truncate regardless
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// of packed vs. unpacked.
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if (IsD16 && !Ty.isVector()) {
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B.buildTrunc(DstReg, ResultRegs[0]);
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return true;
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}
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// Must be an image load.
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if (!ST.hasUnpackedD16VMem() || !Ty.isVector() || Ty.getElementType() != S16)
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// Avoid a build/concat_vector of 1 entry.
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if (Ty == V2S16 && NumDataRegs == 1 && !ST.hasUnpackedD16VMem()) {
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B.buildBitcast(DstReg, ResultRegs[0]);
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return true;
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}
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B.setInsertPt(*MI.getParent(), ++MI.getIterator());
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assert(Ty.isVector());
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LLT WidenedTy = Ty.changeElementType(S32);
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Register WideDstReg = MRI->createGenericVirtualRegister(WidenedTy);
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if (IsD16) {
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// For packed D16 results with TFE enabled, all the data components are
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// S32. Cast back to the expected type.
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//
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// TODO: We don't really need to use load s32 elements. We would only need one
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// cast for the TFE result if a multiple of v2s16 was used.
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if (RegTy != V2S16 && !ST.hasUnpackedD16VMem()) {
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for (Register &Reg : ResultRegs)
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Reg = B.buildBitcast(V2S16, Reg).getReg(0);
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} else if (ST.hasUnpackedD16VMem()) {
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for (Register &Reg : ResultRegs)
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Reg = B.buildTrunc(S16, Reg).getReg(0);
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}
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}
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MI.getOperand(0).setReg(WideDstReg);
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auto padWithUndef = [&](LLT Ty, int NumElts) {
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if (NumElts == 0)
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return;
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Register Undef = B.buildUndef(Ty).getReg(0);
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for (int I = 0; I != NumElts; ++I)
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ResultRegs.push_back(Undef);
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};
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repackUnpackedD16Load(B, DstReg, WideDstReg);
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// Pad out any elements eliminated due to the dmask.
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LLT ResTy = MRI->getType(ResultRegs[0]);
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if (!ResTy.isVector()) {
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padWithUndef(ResTy, NumElts - ResultRegs.size());
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B.buildBuildVector(DstReg, ResultRegs);
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return true;
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}
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assert(!ST.hasUnpackedD16VMem() && ResTy == V2S16);
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const int RegsToCover = (Ty.getSizeInBits() + 31) / 32;
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// Deal with the one annoying legal case.
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const LLT V3S16 = LLT::vector(3, 16);
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if (Ty == V3S16) {
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padWithUndef(ResTy, RegsToCover - ResultRegs.size() + 1);
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auto Concat = B.buildConcatVectors(LLT::vector(6, 16), ResultRegs);
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B.buildUnmerge({DstReg, MRI->createGenericVirtualRegister(V3S16)}, Concat);
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return true;
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}
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padWithUndef(ResTy, RegsToCover - ResultRegs.size());
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B.buildConcatVectors(DstReg, ResultRegs);
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return true;
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}
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@ -2906,12 +2906,12 @@ define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x floa
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; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; GFX9: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
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; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 0, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
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; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
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; GFX9: $vgpr0 = COPY [[UV]](s32)
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; GFX9: $vgpr1 = COPY [[UV1]](s32)
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; GFX9: $vgpr2 = COPY [[UV2]](s32)
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; GFX9: $vgpr3 = COPY [[UV3]](s32)
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; GFX9: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 0, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
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; GFX9: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
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; GFX9: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
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; GFX9: $vgpr1 = COPY [[DEF]](s32)
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; GFX9: $vgpr2 = COPY [[DEF]](s32)
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; GFX9: $vgpr3 = COPY [[DEF]](s32)
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; GFX9: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
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; GFX10NSA-LABEL: name: getresinfo_dmask0
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; GFX10NSA: bb.1.main_body:
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@ -2928,12 +2928,12 @@ define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x floa
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; GFX10NSA: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
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; GFX10NSA: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY8]](<2 x s16>)
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; GFX10NSA: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 0, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
|
||||
; GFX10NSA: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
|
||||
; GFX10NSA: $vgpr0 = COPY [[UV]](s32)
|
||||
; GFX10NSA: $vgpr1 = COPY [[UV1]](s32)
|
||||
; GFX10NSA: $vgpr2 = COPY [[UV2]](s32)
|
||||
; GFX10NSA: $vgpr3 = COPY [[UV3]](s32)
|
||||
; GFX10NSA: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 0, [[TRUNC]](s16), [[BUILD_VECTOR]](<8 x s32>), 0, 0
|
||||
; GFX10NSA: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GFX10NSA: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
||||
; GFX10NSA: $vgpr1 = COPY [[DEF]](s32)
|
||||
; GFX10NSA: $vgpr2 = COPY [[DEF]](s32)
|
||||
; GFX10NSA: $vgpr3 = COPY [[DEF]](s32)
|
||||
; GFX10NSA: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -224,6 +224,587 @@ define amdgpu_ps <4 x float> @image_load_tfe_v4f32(<8 x i32> inreg %rsrc, i32 %s
|
|||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps float @image_load_f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_f32_dmask_0000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 0, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
||||
; GCN: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
|
||||
%tex = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret float %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <2 x float> @image_load_v2f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v2f32_dmask_1000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
||||
%tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <2 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <2 x float> @image_load_v2f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v2f32_dmask_0000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 0, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
||||
%tex = call <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <2 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <3 x float> @image_load_v3f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v3f32_dmask_1100
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[UV1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
%tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <3 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <3 x float> @image_load_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v3f32_dmask_1000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
%tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <3 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <3 x float> @image_load_v3f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v3f32_dmask_0000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 0, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
%tex = call <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <3 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v4f32_dmask_1110
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[UV1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[UV2]](s32)
|
||||
; GCN: $vgpr3 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
%tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v4f32_dmask_1100
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[UV1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF]](s32)
|
||||
; GCN: $vgpr3 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
%tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <4 x float> @image_load_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v4f32_dmask_1000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF]](s32)
|
||||
; GCN: $vgpr3 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
%tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <4 x float> @image_load_v4f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_v4f32_dmask_0000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 0, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
|
||||
; GCN: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF]](s32)
|
||||
; GCN: $vgpr3 = COPY [[DEF]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
%tex = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps float @image_load_tfe_f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_f32_dmask_0000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 0, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 4 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0
|
||||
%res = call { float, i32 } @llvm.amdgcn.image.load.2d.sl_f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { float, i32 } %res, 0
|
||||
%tfe = extractvalue { float, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret float %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <2 x float> @image_load_tfe_v2f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v2f32_dmask_1000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
||||
%res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <2 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <2 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <2 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <2 x float> @image_load_tfe_v2f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v2f32_dmask_0000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 0, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 8 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1
|
||||
%res = call { <2 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v2f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <2 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <2 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <2 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v3f32_dmask_1100
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[UV1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
%res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <3 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <3 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <3 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v3f32_dmask_1000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
%res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <3 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <3 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <3 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <3 x float> @image_load_tfe_v3f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v3f32_dmask_0000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 0, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 12 from custom "TargetCustom8", align 16)
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2
|
||||
%res = call { <3 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v3f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <3 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <3 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <3 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1110(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1110
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 7, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV3]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[UV1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[UV2]](s32)
|
||||
; GCN: $vgpr3 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
%res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <4 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <4 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1100(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1100
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<3 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 3, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<3 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV2]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[UV1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF1]](s32)
|
||||
; GCN: $vgpr3 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
%res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <4 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <4 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v4f32_dmask_1000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 1, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF1]](s32)
|
||||
; GCN: $vgpr3 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
%res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <4 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <4 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
define amdgpu_ps <4 x float> @image_load_tfe_v4f32_dmask_0000(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
; GCN-LABEL: name: image_load_tfe_v4f32_dmask_0000
|
||||
; GCN: bb.1 (%ir-block.0):
|
||||
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2
|
||||
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3
|
||||
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4
|
||||
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5
|
||||
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6
|
||||
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7
|
||||
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8
|
||||
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9
|
||||
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
|
||||
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
|
||||
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32)
|
||||
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 0, [[BUILD_VECTOR1]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), 1, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
|
||||
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x s32>)
|
||||
; GCN: [[DEF1:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
||||
; GCN: G_STORE [[UV1]](s32), [[DEF]](p1) :: (store 4 into `i32 addrspace(1)* undef`, addrspace 1)
|
||||
; GCN: $vgpr0 = COPY [[UV]](s32)
|
||||
; GCN: $vgpr1 = COPY [[DEF1]](s32)
|
||||
; GCN: $vgpr2 = COPY [[DEF1]](s32)
|
||||
; GCN: $vgpr3 = COPY [[DEF1]](s32)
|
||||
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
|
||||
%res = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 0, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0)
|
||||
%tex = extractvalue { <4 x float>, i32 } %res, 0
|
||||
%tfe = extractvalue { <4 x float>, i32 } %res, 1
|
||||
store i32 %tfe, i32 addrspace(1)* undef
|
||||
ret <4 x float> %tex
|
||||
}
|
||||
|
||||
declare float @llvm.amdgcn.image.load.2d.f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
||||
declare <2 x float> @llvm.amdgcn.image.load.2d.v2f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
||||
declare <3 x float> @llvm.amdgcn.image.load.2d.v3f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0
|
||||
|
|
|
|||
Loading…
Reference in New Issue