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[PowerPC] Fix rlwimi isel when mask is not constant 

We had been using the known-zero values of the operand of the or to construct
the mask for an rlwimi; this is not quite correct, but fine when the mask is
constant. When the mask is constant, then the known zeros of the operand must
be a superset of the zeros in the mask. However, when the mask is not a
constant, then there might be bits in the operand that are not known to be zero
that, at runtime, might be zero in the mask. Therefore, we check that any bits
not known to be zero *are* known to be one in the mask. Otherwise, we can't
fold the mask with the or and shift.

This was revealed as a miscompile of
MultiSource/Benchmarks/BitBench/drop3/drop3 when I started experimenting with
constant hoisting.

llvm-svn: 206136
This commit is contained in:
Hal Finkel 2014-04-13 17:10:58 +00:00
parent 6a7ffbed8a
commit d9963c75da
2 changed files with 56 additions and 1 deletions
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9
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -458,8 +458,15 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
} }
if (Op1Opc == ISD::AND) { if (Op1Opc == ISD::AND) {
// The AND mask might not be a constant, and we need to make sure that
// if we're going to fold the masking with the insert, all bits not
// know to be zero in the mask are known to be one.
APInt MKZ, MKO;
CurDAG->ComputeMaskedBits(Op1.getOperand(1), MKZ, MKO);
bool CanFoldMask = InsertMask == MKO.getZExtValue();
unsigned SHOpc = Op1.getOperand(0).getOpcode(); unsigned SHOpc = Op1.getOperand(0).getOpcode();
if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
// Note that Value must be in range here (less than 32) because // Note that Value must be in range here (less than 32) because
// otherwise there would not be any bits set in InsertMask. // otherwise there would not be any bits set in InsertMask.

48
llvm/test/CodeGen/PowerPC/rlwimi-dyn-and.ll Normal file
View File

@ -0,0 +1,48 @@
; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define i32 @test1() #0 {
entry:
%conv67.reload = load i32* undef
%const = bitcast i32 65535 to i32
br label %next
next:
%shl161 = shl nuw nsw i32 %conv67.reload, 15
%0 = load i8* undef, align 1
%conv169 = zext i8 %0 to i32
%shl170 = shl nuw nsw i32 %conv169, 7
%const_mat = add i32 %const, -32767
%shl161.masked = and i32 %shl161, %const_mat
%conv174 = or i32 %shl170, %shl161.masked
ret i32 %conv174
; CHECK-LABEL: @test1
; CHECK-NOT: rlwimi 3, {{[0-9]+}}, 15, 0, 16
; CHECK: blr
}
define i32 @test2() #0 {
entry:
%conv67.reload = load i32* undef
%const = bitcast i32 65535 to i32
br label %next
next:
%shl161 = shl nuw nsw i32 %conv67.reload, 15
%0 = load i8* undef, align 1
%conv169 = zext i8 %0 to i32
%shl170 = shl nuw nsw i32 %conv169, 7
%shl161.masked = and i32 %shl161, 32768
%conv174 = or i32 %shl170, %shl161.masked
ret i32 %conv174
; CHECK-LABEL: @test2
; CHECK: slwi 3, {{[0-9]+}}, 7
; CHECK: rlwimi 3, {{[0-9]+}}, 15, 16, 16
; CHECK: blr
}
attributes #0 = { nounwind }