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[globalisel] Allow SrcOp to convert an APInt and render it as an immediate operand (MO.isImm() == true) 

Summary:
This is tested by D61289 but has been pulled into a separate patch at
a reviewers request.

Reviewers: bogner, aditya_nandakumar, volkan, aemerson, paquette, arsenm, rovka

Reviewed By: arsenm

Subscribers: javed.absar, hiraditya, wdng, kristof.beyls, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61321

llvm-svn: 368063
This commit is contained in:
Daniel Sanders 2019-08-06 17:16:27 +00:00
parent bfbf6b6cab
commit d9934d4939
3 changed files with 25 additions and 3 deletions
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24
llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
View File

@ -122,14 +122,22 @@ class SrcOp {
MachineInstrBuilder SrcMIB;
Register Reg;
CmpInst::Predicate Pred;
int64_t Imm;
};
public:
enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate };
enum class SrcType { Ty_Reg, Ty_MIB, Ty_Predicate, Ty_Imm };
SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {}
SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {}
/// Use of registers held in unsigned integer variables (or more rarely signed
/// integers) is no longer permitted to avoid ambiguity with upcoming support
/// for immediates.
SrcOp(unsigned) = delete;
SrcOp(int) = delete;
SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {}
void addSrcToMIB(MachineInstrBuilder &MIB) const {
switch (Ty) {
@ -142,12 +150,16 @@ public:
case SrcType::Ty_MIB:
MIB.addUse(SrcMIB->getOperand(0).getReg());
break;
case SrcType::Ty_Imm:
MIB.addImm(Imm);
break;
}
}
LLT getLLTTy(const MachineRegisterInfo &MRI) const {
switch (Ty) {
case SrcType::Ty_Predicate:
case SrcType::Ty_Imm:
llvm_unreachable("Not a register operand");
case SrcType::Ty_Reg:
return MRI.getType(Reg);
@ -160,6 +172,7 @@ public:
Register getReg() const {
switch (Ty) {
case SrcType::Ty_Predicate:
case SrcType::Ty_Imm:
llvm_unreachable("Not a register operand");
case SrcType::Ty_Reg:
return Reg;
@ -178,6 +191,15 @@ public:
}
}
int64_t getImm() const {
switch (Ty) {
case SrcType::Ty_Imm:
return Imm;
default:
llvm_unreachable("Not an immediate");
}
}
SrcType getSrcOpKind() const { return Ty; }
private:

2
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -544,7 +544,7 @@ static bool isValidCopy(const MachineInstr &I, const RegisterBank &DstBank,
/// SubRegCopy (To class) = COPY CopyReg:SubReg
/// Dst = COPY SubRegCopy
static bool selectSubregisterCopy(MachineInstr &I, MachineRegisterInfo &MRI,
const RegisterBankInfo &RBI, unsigned SrcReg,
const RegisterBankInfo &RBI, Register SrcReg,
const TargetRegisterClass *From,
const TargetRegisterClass *To,
unsigned SubReg) {

2
llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
View File

@ -686,7 +686,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
// legalized. In order to allow further legalization of the inst, we create
// a new instruction and erase the existing one.
unsigned ValReg = MI.getOperand(0).getReg();
Register ValReg = MI.getOperand(0).getReg();
const LLT ValTy = MRI.getType(ValReg);
if (!ValTy.isVector() || !ValTy.getElementType().isPointer() ||