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[RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec. 

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94580
This commit is contained in:
Craig Topper 2021-01-22 10:47:12 -08:00
parent b2f859500f
commit d985c7321f
2 changed files with 6 additions and 6 deletions
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4
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
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@ -333,8 +333,8 @@ def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>;
let Predicates = [HasStdExtZbb] in {
def MIN : ALU_rr<0b0000101, 0b100, "min">, Sched<[]>;
def MAX : ALU_rr<0b0000101, 0b101, "max">, Sched<[]>;
def MINU : ALU_rr<0b0000101, 0b110, "minu">, Sched<[]>;
def MINU : ALU_rr<0b0000101, 0b101, "minu">, Sched<[]>;
def MAX : ALU_rr<0b0000101, 0b110, "max">, Sched<[]>;
def MAXU : ALU_rr<0b0000101, 0b111, "maxu">, Sched<[]>;
} // Predicates = [HasStdExtZbb]

8
llvm/test/MC/RISCV/rv32zbb-valid.s
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@ -42,12 +42,12 @@ sext.h t0, t1
# CHECK-ASM-AND-OBJ: min t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a]
min t0, t1, t2
# CHECK-ASM-AND-OBJ: max t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
max t0, t1, t2
# CHECK-ASM-AND-OBJ: minu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a]
minu t0, t1, t2
# CHECK-ASM-AND-OBJ: max t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a]
max t0, t1, t2
# CHECK-ASM-AND-OBJ: maxu t0, t1, t2
# CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a]
maxu t0, t1, t2