forked from OSchip/llvm-project
[InstCombine] add tests for shuffle-binop; NFC
This is another pattern mentioned in PR37806. llvm-svn: 336096
This commit is contained in:
Sanjay Patel
parent
265793d52a
commit
d980084597
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@ -4,8 +4,229 @@
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; Try to eliminate binops and shuffles when the shuffle is a select in disguise:
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; PR37806 - https://bugs.llvm.org/show_bug.cgi?id=37806
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define <4 x i32> @add(<4 x i32> %v0) {
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define <4 x i32> @add(<4 x i32> %v) {
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; CHECK-LABEL: @add(
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; CHECK-NEXT: [[B:%.*]] = add <4 x i32> [[V:%.*]], <i32 11, i32 undef, i32 13, i32 undef>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = add <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
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%s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x i32> %s
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}
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; Constant operand 0 (LHS) could work for some non-commutative binops?
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define <4 x i32> @sub(<4 x i32> %v) {
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; CHECK-LABEL: @sub(
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; CHECK-NEXT: [[B:%.*]] = sub <4 x i32> <i32 undef, i32 undef, i32 undef, i32 14>, [[V:%.*]]
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = sub <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
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%s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x i32> %s
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}
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; If any element of the shuffle mask operand is undef, that element of the result is undef.
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; The shuffle is eliminated in this transform, but we can replace a constant element with undef.
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define <4 x i32> @mul(<4 x i32> %v) {
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; CHECK-LABEL: @mul(
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; CHECK-NEXT: [[B:%.*]] = mul <4 x i32> [[V:%.*]], <i32 undef, i32 12, i32 undef, i32 14>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = mul <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
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%s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 undef, i32 5, i32 2, i32 7>
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ret <4 x i32> %s
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}
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; Preserve flags when possible.
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define <4 x i32> @shl(<4 x i32> %v) {
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; CHECK-LABEL: @shl(
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; CHECK-NEXT: [[B:%.*]] = shl nuw <4 x i32> [[V:%.*]], <i32 11, i32 12, i32 13, i32 14>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = shl nuw <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
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%s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 undef, i32 5, i32 2, i32 undef>
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ret <4 x i32> %s
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}
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define <4 x i32> @lshr(<4 x i32> %v) {
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; CHECK-LABEL: @lshr(
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; CHECK-NEXT: [[B:%.*]] = lshr exact <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = lshr exact <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
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%s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
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ret <4 x i32> %s
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}
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; Try weird types.
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define <3 x i32> @ashr(<3 x i32> %v) {
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; CHECK-LABEL: @ashr(
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; CHECK-NEXT: [[B:%.*]] = ashr <3 x i32> [[V:%.*]], <i32 11, i32 12, i32 13>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <3 x i32> [[B]], <3 x i32> [[V]], <3 x i32> <i32 3, i32 1, i32 2>
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; CHECK-NEXT: ret <3 x i32> [[S]]
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;
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%b = ashr <3 x i32> %v, <i32 11, i32 12, i32 13>
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%s = shufflevector <3 x i32> %b, <3 x i32> %v, <3 x i32> <i32 3, i32 1, i32 2>
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ret <3 x i32> %s
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}
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define <3 x i42> @and(<3 x i42> %v) {
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; CHECK-LABEL: @and(
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; CHECK-NEXT: [[B:%.*]] = and <3 x i42> [[V:%.*]], <i42 undef, i42 12, i42 undef>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <3 x i42> [[V]], <3 x i42> [[B]], <3 x i32> <i32 0, i32 4, i32 undef>
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; CHECK-NEXT: ret <3 x i42> [[S]]
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;
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%b = and <3 x i42> %v, <i42 11, i42 12, i42 13>
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%s = shufflevector <3 x i42> %v, <3 x i42> %b, <3 x i32> <i32 0, i32 4, i32 undef>
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ret <3 x i42> %s
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}
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; It doesn't matter if the intermediate op has extra uses.
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declare void @use_v4i32(<4 x i32>)
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define <4 x i32> @or(<4 x i32> %v) {
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; CHECK-LABEL: @or(
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; CHECK-NEXT: [[B:%.*]] = or <4 x i32> [[V:%.*]], <i32 11, i32 12, i32 13, i32 14>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[B]])
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = or <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
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%s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
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call void @use_v4i32(<4 x i32> %b)
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ret <4 x i32> %s
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}
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define <4 x i32> @xor(<4 x i32> %v) {
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; CHECK-LABEL: @xor(
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; CHECK-NEXT: [[B:%.*]] = xor <4 x i32> [[V:%.*]], <i32 undef, i32 12, i32 undef, i32 undef>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = xor <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
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%s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>
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ret <4 x i32> %s
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}
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define <4 x i32> @udiv(<4 x i32> %v) {
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; CHECK-LABEL: @udiv(
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; CHECK-NEXT: [[B:%.*]] = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = udiv <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
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%s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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ret <4 x i32> %s
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}
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; Div/rem need special handling if the shuffle has undef elements.
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define <4 x i32> @sdiv(<4 x i32> %v) {
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; CHECK-LABEL: @sdiv(
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; CHECK-NEXT: [[B:%.*]] = sdiv <4 x i32> [[V:%.*]], <i32 11, i32 12, i32 13, i32 14>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = sdiv <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
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%s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 undef, i32 1, i32 6, i32 undef>
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ret <4 x i32> %s
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}
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define <4 x i32> @urem(<4 x i32> %v) {
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; CHECK-LABEL: @urem(
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; CHECK-NEXT: [[B:%.*]] = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[V]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = urem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
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%s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
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ret <4 x i32> %s
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}
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define <4 x i32> @srem(<4 x i32> %v) {
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; CHECK-LABEL: @srem(
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; CHECK-NEXT: [[B:%.*]] = srem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, [[V:%.*]]
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 0, i32 1, i32 6, i32 3>
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; CHECK-NEXT: ret <4 x i32> [[S]]
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;
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%b = srem <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %v
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%s = shufflevector <4 x i32> %v, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 3>
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ret <4 x i32> %s
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}
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; Try FP ops/types.
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define <4 x float> @fadd(<4 x float> %v) {
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; CHECK-LABEL: @fadd(
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; CHECK-NEXT: [[B:%.*]] = fadd <4 x float> [[V:%.*]], <float 4.100000e+01, float 4.200000e+01, float 4.300000e+01, float 4.400000e+01>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x float> [[B]], <4 x float> [[V]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x float> [[S]]
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;
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%b = fadd <4 x float> %v, <float 41.0, float 42.0, float 43.0, float 44.0>
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%s = shufflevector <4 x float> %b, <4 x float> %v, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x float> %s
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}
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define <4 x double> @fsub(<4 x double> %v) {
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; CHECK-LABEL: @fsub(
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; CHECK-NEXT: [[B:%.*]] = fsub <4 x double> <double 4.100000e+01, double 4.200000e+01, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x double> [[V]], <4 x double> [[B]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x double> [[S]]
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;
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%b = fsub <4 x double> <double 41.0, double 42.0, double 43.0, double 44.0>, %v
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%s = shufflevector <4 x double> %v, <4 x double> %b, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
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ret <4 x double> %s
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}
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; Propagate any FMF.
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define <4 x float> @fmul(<4 x float> %v) {
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; CHECK-LABEL: @fmul(
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; CHECK-NEXT: [[B:%.*]] = fmul nnan ninf <4 x float> [[V:%.*]], <float 4.100000e+01, float 4.200000e+01, float 4.300000e+01, float 4.400000e+01>
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x float> [[B]], <4 x float> [[V]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x float> [[S]]
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;
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%b = fmul nnan ninf <4 x float> %v, <float 41.0, float 42.0, float 43.0, float 44.0>
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%s = shufflevector <4 x float> %b, <4 x float> %v, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
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ret <4 x float> %s
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}
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define <4 x double> @fdiv(<4 x double> %v) {
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; CHECK-LABEL: @fdiv(
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; CHECK-NEXT: [[B:%.*]] = fdiv fast <4 x double> <double 4.100000e+01, double 4.200000e+01, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x double> [[V]], <4 x double> [[B]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x double> [[S]]
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;
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%b = fdiv fast <4 x double> <double 41.0, double 42.0, double 43.0, double 44.0>, %v
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%s = shufflevector <4 x double> %v, <4 x double> %b, <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
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ret <4 x double> %s
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}
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define <4 x double> @frem(<4 x double> %v) {
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; CHECK-LABEL: @frem(
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; CHECK-NEXT: [[B:%.*]] = frem <4 x double> <double 4.100000e+01, double 4.200000e+01, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
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; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x double> [[B]], <4 x double> [[V]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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; CHECK-NEXT: ret <4 x double> [[S]]
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;
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%b = frem <4 x double> <double 41.0, double 42.0, double 43.0, double 44.0>, %v
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%s = shufflevector <4 x double> %b, <4 x double> %v, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
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ret <4 x double> %s
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}
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; Tests where both operands of the shuffle are binops with the same opcode.
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define <4 x i32> @add_add(<4 x i32> %v0) {
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; CHECK-LABEL: @add_add(
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; CHECK-NEXT: [[T3:%.*]] = add <4 x i32> [[V0:%.*]], <i32 1, i32 6, i32 3, i32 8>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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@ -17,8 +238,8 @@ define <4 x i32> @add(<4 x i32> %v0) {
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; Constant operand 0 (LHS) also works.
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define <4 x i32> @sub(<4 x i32> %v0) {
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; CHECK-LABEL: @sub(
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define <4 x i32> @sub_sub(<4 x i32> %v0) {
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; CHECK-LABEL: @sub_sub(
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; CHECK-NEXT: [[T3:%.*]] = sub <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0:%.*]]
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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@ -31,8 +252,8 @@ define <4 x i32> @sub(<4 x i32> %v0) {
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; If any element of the shuffle mask operand is undef, that element of the result is undef.
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; The shuffle is eliminated in this transform, but we can replace a constant element with undef.
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define <4 x i32> @mul(<4 x i32> %v0) {
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; CHECK-LABEL: @mul(
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define <4 x i32> @mul_mul(<4 x i32> %v0) {
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; CHECK-LABEL: @mul_mul(
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; CHECK-NEXT: [[T3:%.*]] = mul <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 8>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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@ -44,8 +265,8 @@ define <4 x i32> @mul(<4 x i32> %v0) {
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; Preserve flags when possible.
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define <4 x i32> @shl(<4 x i32> %v0) {
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; CHECK-LABEL: @shl(
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define <4 x i32> @shl_shl(<4 x i32> %v0) {
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; CHECK-LABEL: @shl_shl(
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; CHECK-NEXT: [[T3:%.*]] = shl nuw <4 x i32> [[V0:%.*]], <i32 undef, i32 6, i32 3, i32 undef>
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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@ -57,8 +278,8 @@ define <4 x i32> @shl(<4 x i32> %v0) {
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; Can't propagate the flag here.
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define <4 x i32> @lshr(<4 x i32> %v0) {
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; CHECK-LABEL: @lshr(
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define <4 x i32> @lshr_lshr(<4 x i32> %v0) {
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; CHECK-LABEL: @lshr_lshr(
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; CHECK-NEXT: [[T3:%.*]] = lshr <4 x i32> <i32 5, i32 6, i32 3, i32 8>, [[V0:%.*]]
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; CHECK-NEXT: ret <4 x i32> [[T3]]
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;
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@ -70,8 +291,8 @@ define <4 x i32> @lshr(<4 x i32> %v0) {
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; Try weird types.
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define <3 x i32> @ashr(<3 x i32> %v0) {
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; CHECK-LABEL: @ashr(
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define <3 x i32> @ashr_ashr(<3 x i32> %v0) {
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; CHECK-LABEL: @ashr_ashr(
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; CHECK-NEXT: [[T3:%.*]] = ashr <3 x i32> [[V0:%.*]], <i32 4, i32 2, i32 3>
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; CHECK-NEXT: ret <3 x i32> [[T3]]
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;
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@ -81,8 +302,8 @@ define <3 x i32> @ashr(<3 x i32> %v0) {
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ret <3 x i32> %t3
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}
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define <3 x i42> @and(<3 x i42> %v0) {
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; CHECK-LABEL: @and(
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define <3 x i42> @and_and(<3 x i42> %v0) {
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; CHECK-LABEL: @and_and(
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; CHECK-NEXT: [[T3:%.*]] = and <3 x i42> [[V0:%.*]], <i42 1, i42 5, i42 undef>
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; CHECK-NEXT: ret <3 x i42> [[T3]]
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||||
;
|
||||
|
|
@ -94,10 +315,8 @@ define <3 x i42> @and(<3 x i42> %v0) {
|
|||
|
||||
; It doesn't matter if the intermediate ops have extra uses.
|
||||
|
||||
declare void @use_v4i32(<4 x i32>)
|
||||
|
||||
define <4 x i32> @or(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @or(
|
||||
define <4 x i32> @or_or(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @or_or(
|
||||
; CHECK-NEXT: [[T1:%.*]] = or <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 3, i32 4>
|
||||
; CHECK-NEXT: [[T3:%.*]] = or <4 x i32> [[V0]], <i32 5, i32 6, i32 3, i32 4>
|
||||
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T1]])
|
||||
|
|
@ -110,8 +329,8 @@ define <4 x i32> @or(<4 x i32> %v0) {
|
|||
ret <4 x i32> %t3
|
||||
}
|
||||
|
||||
define <4 x i32> @xor(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @xor(
|
||||
define <4 x i32> @xor_xor(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @xor_xor(
|
||||
; CHECK-NEXT: [[T2:%.*]] = xor <4 x i32> [[V0:%.*]], <i32 5, i32 6, i32 7, i32 8>
|
||||
; CHECK-NEXT: [[T3:%.*]] = xor <4 x i32> [[V0]], <i32 1, i32 6, i32 3, i32 4>
|
||||
; CHECK-NEXT: call void @use_v4i32(<4 x i32> [[T2]])
|
||||
|
|
@ -124,8 +343,8 @@ define <4 x i32> @xor(<4 x i32> %v0) {
|
|||
ret <4 x i32> %t3
|
||||
}
|
||||
|
||||
define <4 x i32> @udiv(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @udiv(
|
||||
define <4 x i32> @udiv_udiv(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @udiv_udiv(
|
||||
; CHECK-NEXT: [[T1:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
|
||||
; CHECK-NEXT: [[T2:%.*]] = udiv <4 x i32> <i32 5, i32 6, i32 7, i32 8>, [[V0]]
|
||||
; CHECK-NEXT: [[T3:%.*]] = udiv <4 x i32> <i32 1, i32 2, i32 3, i32 8>, [[V0]]
|
||||
|
|
@ -143,8 +362,8 @@ define <4 x i32> @udiv(<4 x i32> %v0) {
|
|||
|
||||
; Div/rem need special handling if the shuffle has undef elements.
|
||||
|
||||
define <4 x i32> @sdiv(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @sdiv(
|
||||
define <4 x i32> @sdiv_sdiv(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @sdiv_sdiv(
|
||||
; CHECK-NEXT: [[T3:%.*]] = sdiv <4 x i32> [[V0:%.*]], <i32 1, i32 2, i32 7, i32 1>
|
||||
; CHECK-NEXT: ret <4 x i32> [[T3]]
|
||||
;
|
||||
|
|
@ -154,8 +373,8 @@ define <4 x i32> @sdiv(<4 x i32> %v0) {
|
|||
ret <4 x i32> %t3
|
||||
}
|
||||
|
||||
define <4 x i32> @urem(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @urem(
|
||||
define <4 x i32> @urem_urem(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @urem_urem(
|
||||
; CHECK-NEXT: [[T3:%.*]] = urem <4 x i32> <i32 1, i32 2, i32 7, i32 1>, [[V0:%.*]]
|
||||
; CHECK-NEXT: ret <4 x i32> [[T3]]
|
||||
;
|
||||
|
|
@ -165,8 +384,8 @@ define <4 x i32> @urem(<4 x i32> %v0) {
|
|||
ret <4 x i32> %t3
|
||||
}
|
||||
|
||||
define <4 x i32> @srem(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @srem(
|
||||
define <4 x i32> @srem_srem(<4 x i32> %v0) {
|
||||
; CHECK-LABEL: @srem_srem(
|
||||
; CHECK-NEXT: [[T3:%.*]] = srem <4 x i32> <i32 1, i32 2, i32 7, i32 4>, [[V0:%.*]]
|
||||
; CHECK-NEXT: ret <4 x i32> [[T3]]
|
||||
;
|
||||
|
|
@ -178,8 +397,8 @@ define <4 x i32> @srem(<4 x i32> %v0) {
|
|||
|
||||
; Try FP ops/types.
|
||||
|
||||
define <4 x float> @fadd(<4 x float> %v0) {
|
||||
; CHECK-LABEL: @fadd(
|
||||
define <4 x float> @fadd_fadd(<4 x float> %v0) {
|
||||
; CHECK-LABEL: @fadd_fadd(
|
||||
; CHECK-NEXT: [[T3:%.*]] = fadd <4 x float> [[V0:%.*]], <float 1.000000e+00, float 2.000000e+00, float 7.000000e+00, float 8.000000e+00>
|
||||
; CHECK-NEXT: ret <4 x float> [[T3]]
|
||||
;
|
||||
|
|
@ -189,8 +408,8 @@ define <4 x float> @fadd(<4 x float> %v0) {
|
|||
ret <4 x float> %t3
|
||||
}
|
||||
|
||||
define <4 x double> @fsub(<4 x double> %v0) {
|
||||
; CHECK-LABEL: @fsub(
|
||||
define <4 x double> @fsub_fsub(<4 x double> %v0) {
|
||||
; CHECK-LABEL: @fsub_fsub(
|
||||
; CHECK-NEXT: [[T3:%.*]] = fsub <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
|
||||
; CHECK-NEXT: ret <4 x double> [[T3]]
|
||||
;
|
||||
|
|
@ -202,8 +421,8 @@ define <4 x double> @fsub(<4 x double> %v0) {
|
|||
|
||||
; Intersect any FMF.
|
||||
|
||||
define <4 x float> @fmul(<4 x float> %v0) {
|
||||
; CHECK-LABEL: @fmul(
|
||||
define <4 x float> @fmul_fmul(<4 x float> %v0) {
|
||||
; CHECK-LABEL: @fmul_fmul(
|
||||
; CHECK-NEXT: [[T3:%.*]] = fmul nnan ninf <4 x float> [[V0:%.*]], <float 1.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00>
|
||||
; CHECK-NEXT: ret <4 x float> [[T3]]
|
||||
;
|
||||
|
|
@ -213,8 +432,8 @@ define <4 x float> @fmul(<4 x float> %v0) {
|
|||
ret <4 x float> %t3
|
||||
}
|
||||
|
||||
define <4 x double> @fdiv(<4 x double> %v0) {
|
||||
; CHECK-LABEL: @fdiv(
|
||||
define <4 x double> @fdiv_fdiv(<4 x double> %v0) {
|
||||
; CHECK-LABEL: @fdiv_fdiv(
|
||||
; CHECK-NEXT: [[T3:%.*]] = fdiv nnan arcp <4 x double> <double undef, double 2.000000e+00, double 7.000000e+00, double 8.000000e+00>, [[V0:%.*]]
|
||||
; CHECK-NEXT: ret <4 x double> [[T3]]
|
||||
;
|
||||
|
|
@ -226,8 +445,8 @@ define <4 x double> @fdiv(<4 x double> %v0) {
|
|||
|
||||
; The variable operand must be either the first operand or second operand in both binops.
|
||||
|
||||
define <4 x double> @frem(<4 x double> %v0) {
|
||||
; CHECK-LABEL: @frem(
|
||||
define <4 x double> @frem_frem(<4 x double> %v0) {
|
||||
; CHECK-LABEL: @frem_frem(
|
||||
; CHECK-NEXT: [[T1:%.*]] = frem <4 x double> <double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00>, [[V0:%.*]]
|
||||
; CHECK-NEXT: [[T2:%.*]] = frem <4 x double> [[V0]], <double 5.000000e+00, double 6.000000e+00, double 7.000000e+00, double 8.000000e+00>
|
||||
; CHECK-NEXT: [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
|
||||
|
|
|
|||
Loading…
Reference in New Issue