From d9790793d60978c72436a588204130d7be09a04f Mon Sep 17 00:00:00 2001 From: Zoran Jovanovic Date: Wed, 9 Sep 2015 09:10:46 +0000 Subject: [PATCH] [mips][microMIPS] Implement CACHEE and PREFE instructions Differential Revision: http://reviews.llvm.org/D11628 llvm-svn: 247125 --- .../Mips/Disassembler/MipsDisassembler.cpp | 22 +++++++++++++++++++ .../lib/Target/Mips/MicroMips32r6InstrInfo.td | 8 ------- llvm/lib/Target/Mips/MicroMipsInstrFormats.td | 16 ++++++++++++++ llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 15 +++++++++++++ llvm/test/MC/Disassembler/Mips/micromips.txt | 4 ++++ .../MC/Disassembler/Mips/micromips_le.txt | 4 ++++ .../MC/Mips/micromips-control-instructions.s | 6 +++++ 7 files changed, 67 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index cbf9e1356bc5..c51a4f0927a4 100644 --- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -261,6 +261,11 @@ static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodePrefeOpMM(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1152,6 +1157,23 @@ static DecodeStatus DecodeCacheOpMM(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodePrefeOpMM(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<9>(Insn & 0x1ff); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Hint = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + Inst.addOperand(MCOperand::createImm(Hint)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeCacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 1cdf0de275fe..2d73f80de7b8 100644 --- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -11,14 +11,6 @@ // //===----------------------------------------------------------------------===// -def mem_mm_9 : Operand { - let PrintMethod = "printMemOperand"; - let MIOperandInfo = (ops GPR32, simm9); - let EncoderMethod = "getMemEncodingMMImm9"; - let ParserMatchClass = MipsMemAsmOperand; - let OperandType = "OPERAND_MEMORY"; -} - //===----------------------------------------------------------------------===// // // Instruction Encodings diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td index 560afa48908c..161de310ab51 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td @@ -922,6 +922,22 @@ class CACHE_PREF_FM_MM op, bits<4> funct> : MMArch { let Inst{11-0} = offset; } +class CACHE_PREFE_FM_MM op, bits<3> funct> : MMArch { + bits<21> addr; + bits<5> hint; + bits<5> base = addr{20-16}; + bits<9> offset = addr{8-0}; + + bits<32> Inst; + + let Inst{31-26} = op; + let Inst{25-21} = hint; + let Inst{20-16} = base; + let Inst{15-12} = 0xA; + let Inst{11-9} = funct; + let Inst{8-0} = offset; +} + class BARRIER_FM_MM op> : MMArch { bits<32> Inst; diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 619f9f6dcf6b..a9bcb8e3536a 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -105,6 +105,14 @@ def mem_mm_gp_imm7_lsl2 : Operand { let EncoderMethod = "getMemEncodingMMGPImm7Lsl2"; } +def mem_mm_9 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops GPR32, simm9); + let EncoderMethod = "getMemEncodingMMImm9"; + let ParserMatchClass = MipsMemAsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + def mem_mm_12 : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR32, simm12); @@ -860,6 +868,13 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>, CACHE_PREF_FM_MM<0x18, 0x2>; } + + let DecoderMethod = "DecodePrefeOpMM" in { + def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>, + CACHE_PREFE_FM_MM<0x18, 0x2>; + def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>, + CACHE_PREFE_FM_MM<0x18, 0x3>; + } def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>; def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>; def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>; diff --git a/llvm/test/MC/Disassembler/Mips/micromips.txt b/llvm/test/MC/Disassembler/Mips/micromips.txt index 5809ac28113c..71768307879f 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips.txt @@ -340,3 +340,7 @@ 0x00 0x00 0x57 0x7c # CHECK: ei 0x00 0x0a 0x57 0x7c # CHECK: ei $10 + +0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5) + +0x60 0x25 0xa4 0x08 # CHECK: prefe 1, 8($5) diff --git a/llvm/test/MC/Disassembler/Mips/micromips_le.txt b/llvm/test/MC/Disassembler/Mips/micromips_le.txt index 3058bd061066..48046f8d1d45 100644 --- a/llvm/test/MC/Disassembler/Mips/micromips_le.txt +++ b/llvm/test/MC/Disassembler/Mips/micromips_le.txt @@ -340,3 +340,7 @@ 0x00 0x00 0x7c 0x57 # CHECK: ei 0x0a 0x00 0x7c 0x57 # CHECK: ei $10 + +0x25 0x60 0x08 0xa6 # CHECK: cachee 1, 8($5) + +0x25 0x60 0x08 0xa4 # CHECK: prefe 1, 8($5) diff --git a/llvm/test/MC/Mips/micromips-control-instructions.s b/llvm/test/MC/Mips/micromips-control-instructions.s index 76c953f85d55..5e42a6072a98 100644 --- a/llvm/test/MC/Mips/micromips-control-instructions.s +++ b/llvm/test/MC/Mips/micromips-control-instructions.s @@ -39,6 +39,8 @@ # CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13] # CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23] # CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33] +# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4] +# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -72,6 +74,8 @@ # CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c] # CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c] # CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c] +# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08] +# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08] sdbbp sdbbp 34 @@ -100,3 +104,5 @@ tlbr tlbwi tlbwr + prefe 1, 8($5) + cachee 1, 8($5)