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[ARM] Extra MVE-related testing. 

This adds some extra RUN lines to existing test files, to check that
things that worked in previous architecture versions haven't
accidentally stopped working in 8.1-M. Also we add some new tests: a
test of scalar floating point instructions that could be easily
confused with the similar-looking vector ones at assembly time, a test
of basic load/store/move access to the FP registers (which has to work
even in integer-only MVE); and one final check of the really obvious
case where turning off MVE should make sure MVE instructions really
are rejected.

Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover

Subscribers: javed.absar, kristof.beyls, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62682

llvm-svn: 364293
This commit is contained in:
Simon Tatham 2019-06-25 11:24:42 +00:00
parent 86b7a1e660
commit d9654723ad
6 changed files with 179 additions and 10 deletions
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140
llvm/test/MC/ARM/fp-armv8-m.s Normal file
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@ -0,0 +1,140 @@
@ RUN: llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp -mattr=+fp64 -show-encoding < %s \
@ RUN: | FileCheck --check-prefix=CHECK-V81M %s
@ RUN: llvm-mc -triple thumbv8.1m.main -mattr=+fp-armv8 -mattr=+fp64 -show-encoding < %s \
@ RUN: | FileCheck --check-prefix=CHECK-V81M %s
@ VCVT{B,T}
vcvtt.f64.f16 d3, s1
@ CHECK-V81M: vcvtt.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
vcvtt.f16.f64 s5, d12
@ CHECK-V81M: vcvtt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b]
vcvtb.f64.f16 d3, s1
@ CHECK-V81M: vcvtb.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
vcvtb.f16.f64 s4, d1
@ CHECK-V81M: vcvtb.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
it ge
vcvttge.f64.f16 d3, s1
@ CHECK-V81M: vcvttge.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0xe0,0x3b]
it gt
vcvttgt.f16.f64 s5, d12
@ CHECK-V81M: vcvttgt.f16.f64 s5, d12 @ encoding: [0xf3,0xee,0xcc,0x2b]
it eq
vcvtbeq.f64.f16 d3, s1
@ CHECK-V81M: vcvtbeq.f64.f16 d3, s1 @ encoding: [0xb2,0xee,0x60,0x3b]
it lt
vcvtblt.f16.f64 s4, d1
@ CHECK-V81M: vcvtblt.f16.f64 s4, d1 @ encoding: [0xb3,0xee,0x41,0x2b]
@ VCVT{A,N,P,M}
vcvta.s32.f32 s2, s3
@ CHECK-V81M: vcvta.s32.f32 s2, s3 @ encoding: [0xbc,0xfe,0xe1,0x1a]
vcvta.s32.f64 s2, d3
@ CHECK-V81M: vcvta.s32.f64 s2, d3 @ encoding: [0xbc,0xfe,0xc3,0x1b]
vcvtn.s32.f32 s6, s23
@ CHECK-V81M: vcvtn.s32.f32 s6, s23 @ encoding: [0xbd,0xfe,0xeb,0x3a]
vcvtn.s32.f64 s6, d7
@ CHECK-V81M: vcvtn.s32.f64 s6, d7 @ encoding: [0xbd,0xfe,0xc7,0x3b]
vcvtp.s32.f32 s0, s4
@ CHECK-V81M: vcvtp.s32.f32 s0, s4 @ encoding: [0xbe,0xfe,0xc2,0x0a]
vcvtp.s32.f64 s0, d4
@ CHECK-V81M: vcvtp.s32.f64 s0, d4 @ encoding: [0xbe,0xfe,0xc4,0x0b]
vcvtm.s32.f32 s17, s8
@ CHECK-V81M: vcvtm.s32.f32 s17, s8 @ encoding: [0xff,0xfe,0xc4,0x8a]
vcvtm.s32.f64 s17, d8
@ CHECK-V81M: vcvtm.s32.f64 s17, d8 @ encoding: [0xff,0xfe,0xc8,0x8b]
vcvta.u32.f32 s2, s3
@ CHECK-V81M: vcvta.u32.f32 s2, s3 @ encoding: [0xbc,0xfe,0x61,0x1a]
vcvta.u32.f64 s2, d3
@ CHECK-V81M: vcvta.u32.f64 s2, d3 @ encoding: [0xbc,0xfe,0x43,0x1b]
vcvtn.u32.f32 s6, s23
@ CHECK-V81M: vcvtn.u32.f32 s6, s23 @ encoding: [0xbd,0xfe,0x6b,0x3a]
vcvtn.u32.f64 s6, d7
@ CHECK-V81M: vcvtn.u32.f64 s6, d7 @ encoding: [0xbd,0xfe,0x47,0x3b]
vcvtp.u32.f32 s0, s4
@ CHECK-V81M: vcvtp.u32.f32 s0, s4 @ encoding: [0xbe,0xfe,0x42,0x0a]
vcvtp.u32.f64 s0, d4
@ CHECK-V81M: vcvtp.u32.f64 s0, d4 @ encoding: [0xbe,0xfe,0x44,0x0b]
vcvtm.u32.f32 s17, s8
@ CHECK-V81M: vcvtm.u32.f32 s17, s8 @ encoding: [0xff,0xfe,0x44,0x8a]
vcvtm.u32.f64 s17, d8
@ CHECK-V81M: vcvtm.u32.f64 s17, d8 @ encoding: [0xff,0xfe,0x48,0x8b]
@ VSEL
vselge.f32 s4, s1, s23
@ CHECK-V81M: vselge.f32 s4, s1, s23 @ encoding: [0x20,0xfe,0xab,0x2a]
vselge.f64 d0, d1, d3
@ CHECK-V81M: vselge.f64 d0, d1, d3 @ encoding: [0x21,0xfe,0x03,0x0b]
vselgt.f32 s0, s1, s0
@ CHECK-V81M: vselgt.f32 s0, s1, s0 @ encoding: [0x30,0xfe,0x80,0x0a]
vselgt.f64 d5, d10, d11
@ CHECK-V81M: vselgt.f64 d5, d10, d11 @ encoding: [0x3a,0xfe,0x0b,0x5b]
vseleq.f32 s30, s28, s23
@ CHECK-V81M: vseleq.f32 s30, s28, s23 @ encoding: [0x0e,0xfe,0x2b,0xfa]
vseleq.f64 d2, d4, d8
@ CHECK-V81M: vseleq.f64 d2, d4, d8 @ encoding: [0x04,0xfe,0x08,0x2b]
vselvs.f32 s21, s16, s14
@ CHECK-V81M: vselvs.f32 s21, s16, s14 @ encoding: [0x58,0xfe,0x07,0xaa]
vselvs.f64 d0, d1, d15
@ CHECK-V81M: vselvs.f64 d0, d1, d15 @ encoding: [0x11,0xfe,0x0f,0x0b]
@ VMAXNM / VMINNM
vmaxnm.f32 s5, s12, s0
@ CHECK-V81M: vmaxnm.f32 s5, s12, s0 @ encoding: [0xc6,0xfe,0x00,0x2a]
vmaxnm.f64 d5, d14, d15
@ CHECK-V81M: vmaxnm.f64 d5, d14, d15 @ encoding: [0x8e,0xfe,0x0f,0x5b]
vminnm.f32 s0, s0, s12
@ CHECK-V81M: vminnm.f32 s0, s0, s12 @ encoding: [0x80,0xfe,0x46,0x0a]
vminnm.f64 d4, d6, d9
@ CHECK-V81M: vminnm.f64 d4, d6, d9 @ encoding: [0x86,0xfe,0x49,0x4b]
@ VRINT{Z,R,X}
it ge
vrintzge.f64 d3, d12
@ CHECK-V81M: vrintzge.f64 d3, d12 @ encoding: [0xb6,0xee,0xcc,0x3b]
vrintz.f32 s3, s24
@ CHECK-V81M: vrintz.f32 s3, s24 @ encoding: [0xf6,0xee,0xcc,0x1a]
it lt
vrintrlt.f64 d5, d0
@ CHECK-V81M: vrintrlt.f64 d5, d0 @ encoding: [0xb6,0xee,0x40,0x5b]
vrintr.f32 s0, s9
@ CHECK-V81M: vrintr.f32 s0, s9 @ encoding: [0xb6,0xee,0x64,0x0a]
it eq
vrintxeq.f64 d14, d15
@ CHECK-V81M: vrintxeq.f64 d14, d15 @ encoding: [0xb7,0xee,0x4f,0xeb]
it vs
vrintxvs.f32 s10, s14
@ CHECK-V81M: vrintxvs.f32 s10, s14 @ encoding: [0xb7,0xee,0x47,0x5a]
@ VRINT{A,N,P,M}
vrinta.f64 d3, d4
@ CHECK-V81M: vrinta.f64 d3, d4 @ encoding: [0xb8,0xfe,0x44,0x3b]
vrinta.f32 s12, s1
@ CHECK-V81M: vrinta.f32 s12, s1 @ encoding: [0xb8,0xfe,0x60,0x6a]
vrintn.f64 d3, d4
@ CHECK-V81M: vrintn.f64 d3, d4 @ encoding: [0xb9,0xfe,0x44,0x3b]
vrintn.f32 s12, s1
@ CHECK-V81M: vrintn.f32 s12, s1 @ encoding: [0xb9,0xfe,0x60,0x6a]
vrintp.f64 d3, d4
@ CHECK-V81M: vrintp.f64 d3, d4 @ encoding: [0xba,0xfe,0x44,0x3b]
vrintp.f32 s12, s1
@ CHECK-V81M: vrintp.f32 s12, s1 @ encoding: [0xba,0xfe,0x60,0x6a]
vrintm.f64 d3, d4
@ CHECK-V81M: vrintm.f64 d3, d4 @ encoding: [0xbb,0xfe,0x44,0x3b]
vrintm.f32 s12, s1
@ CHECK-V81M: vrintm.f32 s12, s1 @ encoding: [0xbb,0xfe,0x60,0x6a]
@ MVFR2
vmrs sp, mvfr2
@ CHECK-V81M: vmrs sp, mvfr2 @ encoding: [0xf5,0xee,0x10,0xda]

2
llvm/test/MC/ARM/fullfp16.s
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@ -1,5 +1,7 @@
@ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=ARM
@ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -show-encoding < %s | FileCheck %s --check-prefix=THUMB
@ RUN llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=THUMB
@ RUN llvm-mc -triple thumbv8.1m.main -mattr=+fullfp16 -show-encoding < %s | FileCheck %s --check-prefix=THUMB
vadd.f16 s0, s1, s0
@ ARM: vadd.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x30,0xee]

25
llvm/test/MC/ARM/mve-fp-registers.s
View File

@ -15,27 +15,32 @@
// VFP and NEON implementations by default have FP32 and FP64, but not FP16.
// The VFPv3 FP16 extension just added conversion instructions, which we don't
// care about here.
// RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp2 2>%t < %s | \
// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
// RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp2 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
// RUN: FileCheck %s < %t --check-prefix=NOFP16
// RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+fp-armv8,+neon 2>%t < %s | \
// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
// RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+fp-armv8,+neon 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
// RUN: FileCheck %s < %t --check-prefix=NOFP16
// The v8.2A FP16 extension added loads, stores and moves for FP16.
// RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+fp-armv8,+fullfp16 < %s | \
// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
// RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+fp-armv8,+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
// M-profile FPUs (e.g. Cortex-M4/M7/M33) do not have FP16 instructions, and
// the FP64 instructions are optional. They are also limited to 16 D registers,
// but we don't test that here.
// RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4d16sp 2>%t < %s | \
// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=FP32
// RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4d16sp 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32
// RUN: FileCheck %s < %t --check-prefix=NOFP16 --check-prefix=NOFP64
// RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4,-d32 2>%t < %s | \
// RUN: FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
// RUN: not llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+vfp4,-d32 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP32 --check-prefix=FP64
// RUN: FileCheck %s < %t --check-prefix=NOFP16
// Integer-only MVE, which can be combined with different options for scalar
// FPU (or lack thereof), and has all of the move and store instructions
// regardless of the scalar FPU.
// RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+mve 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
// RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+mve,+fp-armv8-sp,+fullfp16 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
// RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+mve,+fp-armv8,+fullfp16 2>%t < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
// Maximal v8.1M target: MVE with FP, and scalar FP with double-precision.
// RUN: llvm-mc -triple=thumbv8.1m.main -show-encoding -mattr=+mve.fp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16 --check-prefix=FP32 --check-prefix=FP64
vldmia r0, {d0}
# FP32: vldmia r0, {d0} @ encoding: [0x90,0xec,0x02,0x0b]
# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers

16
llvm/test/MC/ARM/no-mve.s Normal file
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@ -0,0 +1,16 @@
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t
# RUN: FileCheck < %t %s
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s &>%t
# RUN: FileCheck --check-prefix=CHECK-MVE < %t %s
# CHECK-MVE: instruction requires: mve.fp
# CHECK: invalid instruction
vcadd.f32 q1, q2, q3, #270
# CHECK-MVE: instruction requires: mve.fp
# CHECK: invalid instruction
vadd.f32 q1, q2, q3
# CHECK-MVE: vadd.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x46,0x28]
# CHECK: invalid instruction
vadd.i16 q1, q2, q3

3
llvm/test/MC/ARM/ras-extension.s
View File

@ -1,6 +1,9 @@
@ RUN: llvm-mc -triple armv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=ARM
@ RUN: llvm-mc -triple thumbv8a-none-eabi -mattr=+ras -show-encoding %s | FileCheck %s --check-prefix=THUMB
@ RUN: llvm-mc -triple thumbv8.1m.main-none-eabi -show-encoding %s | FileCheck %s --check-prefix=THUMB
@ RUN: not llvm-mc -triple thumbv8m-none-eabi -show-encoding %s 2>&1 | FileCheck %s --check-prefix=FAIL
esb
@ ARM: esb @ encoding: [0x10,0xf0,0x20,0xe3]
@ THUMB: esb.w @ encoding: [0xaf,0xf3,0x10,0x80]
@ FAIL: instruction requires: ras

3
llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt
View File

@ -1,6 +1,9 @@
# RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=+ras -disassemble | FileCheck %s --check-prefix=RAS
# RUN: llvm-mc < %s -triple thumbv8a-none-eabi -mattr=-ras -disassemble | FileCheck %s --check-prefix=NO-RAS
# RUN: llvm-mc < %s -triple=thumbv8.1m.main-none-eabi -disassemble | FileCheck %s --check-prefix=RAS
# RUN: not llvm-mc < %s -triple=thumbv8m-none-eabi -disassemble 2>&1 | FileCheck %s --check-prefix=FAIL
[0xaf,0xf3,0x10,0x80]
# RAS: esb
# NO-RAS: hint.w #16
# FAIL: invalid instruction encoding